Defined in 37 files as a member:
- contrib/llvm-project/llvm/include/llvm/CodeGen/CalcSpillWeights.h, line 52 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/LiveInterval.h, line 993 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/LiveRangeEdit.h, line 73 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/LiveRegMatrix.h, line 42 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachinePipeliner.h, line 124 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineScheduler.h, line 125 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineScheduler.h, line 268 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/ModuloSchedule.h, line 173 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/ModuloSchedule.h, line 298 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/RegAllocPBQP.h, line 143 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/RegisterPressure.h, line 363 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/InlineSpiller.cpp, line 88 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/InlineSpiller.cpp, line 161 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/InterferenceCache.h, line 63 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/LiveDebugVariables.cpp, line 394 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/LiveIntervals.cpp, line 954 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/ModuloSchedule.cpp, line 1258 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/PHIElimination.cpp, line 70 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/RegAllocBase.h, line 67 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 131 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 2244 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/RenameIndependentSubregs.cpp, line 104 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/SplitKit.h, line 52 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/SplitKit.h, line 100 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/SplitKit.h, line 261 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 98 (as a member)
- contrib/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp, line 181 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp, line 80 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp, line 150 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h, line 111 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, line 88 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp, line 52 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp, line 41 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 155 (as a member)
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, line 169 (as a member)
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp, line 46 (as a member)
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp, line 67 (as a member)
Referenced in 86 files:
- contrib/llvm-project/clang/lib/Sema/SemaOpenMP.cpp
- contrib/llvm-project/llvm/include/llvm/CodeGen/CalcSpillWeights.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/LiveInterval.h, line 997
- contrib/llvm-project/llvm/include/llvm/CodeGen/LiveRangeEdit.h, line 142
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachinePipeliner.h, line 205
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineScheduler.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/ModuloSchedule.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/RegAllocPBQP.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/RegisterPressure.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h, line 313
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 964
- contrib/llvm-project/llvm/lib/CodeGen/CalcSpillWeights.cpp
- contrib/llvm-project/llvm/lib/CodeGen/InlineSpiller.cpp
- contrib/llvm-project/llvm/lib/CodeGen/InterferenceCache.cpp
- contrib/llvm-project/llvm/lib/CodeGen/InterferenceCache.h, line 108
- contrib/llvm-project/llvm/lib/CodeGen/LiveDebugVariables.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveDebugVariables.h, line 45
- contrib/llvm-project/llvm/lib/CodeGen/LiveInterval.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveIntervals.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveRangeEdit.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveRegMatrix.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineBasicBlock.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp
- contrib/llvm-project/llvm/lib/CodeGen/ModuloSchedule.cpp
- contrib/llvm-project/llvm/lib/CodeGen/PHIElimination.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegAllocBase.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegAllocBasic.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegAllocGreedy.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegAllocPBQP.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegisterPressure.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
- contrib/llvm-project/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm-project/llvm/lib/CodeGen/SplitKit.cpp
- contrib/llvm-project/llvm/lib/CodeGen/SplitKit.h
- contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm-project/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
- contrib/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, line 3478
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.h, line 177
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.h
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, line 7110
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h, line 1050
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 851
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h, line 209
- contrib/llvm-project/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AVR/AVRRegisterInfo.h, line 60
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h, line 61
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCFastISel.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp, line 84
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h, line 88
- contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
- contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
- contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.h