Defined in 1 files as a prototype:

• contrib/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h, line 1661 (as a prototype)

Defined in 1 files as a function:

• contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp, line 296 (as a function)

Referenced in 60 files:

• contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp
  • line 612
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• contrib/llvm-project/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
  • line 100
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• contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp, line 2368
• contrib/llvm-project/llvm/lib/CodeGen/InlineSpiller.cpp
  • line 899
  • line 1533
• contrib/llvm-project/llvm/lib/CodeGen/LiveRangeEdit.cpp, line 356
• contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp
  • line 1868
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• contrib/llvm-project/llvm/lib/CodeGen/MachineLoopUtils.cpp
  • line 93
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  • line 100
  • line 101
• contrib/llvm-project/llvm/lib/CodeGen/ModuloSchedule.cpp
  • line 840
  • line 841
  • line 1961
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• contrib/llvm-project/llvm/lib/CodeGen/PeepholeOptimizer.cpp, line 1007
• contrib/llvm-project/llvm/lib/CodeGen/ProcessImplicitDefs.cpp, line 127
• contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 1604
• contrib/llvm-project/llvm/lib/CodeGen/TailDuplicator.cpp
  • line 371
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  • line 497
  • line 498
  • line 543
  • line 544
• contrib/llvm-project/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 1616
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• contrib/llvm-project/llvm/lib/CodeGen/UnreachableBlockElim.cpp
  • line 136
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• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
  • line 250
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• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, line 1242
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SLSHardening.cpp
  • line 359
  • line 360
• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  • line 99
  • line 655
• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  • line 3780
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  • line 274
  • line 697
  • line 727
  • line 828
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  • line 10989
  • line 11007
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 2526
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  • line 2644
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, line 566
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp, line 192
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp, line 306
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 859
• contrib/llvm-project/llvm/lib/Target/ARC/ARCOptAddrMode.cpp
  • line 451
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  • line 1674
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  • line 5029
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp
  • line 11333
  • line 11371
• contrib/llvm-project/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
  • line 738
  • line 753
  • line 1002
• contrib/llvm-project/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  • line 501
  • line 538
  • line 572
• contrib/llvm-project/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, line 341
• contrib/llvm-project/llvm/lib/Target/AVR/AVRRegisterInfo.cpp, line 159
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp, line 1999
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  • line 873
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  • line 2520
  • line 3177
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  • line 829
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• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, line 698
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
  • line 1932
  • line 1933
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp, line 1624
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
  • line 218
  • line 225
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp, line 204
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp, line 220
• contrib/llvm-project/llvm/lib/Target/Mips/MipsBranchExpansion.cpp, line 722
• contrib/llvm-project/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
  • line 1662
  • line 1663
• contrib/llvm-project/llvm/lib/Target/Mips/MipsInstrInfo.cpp, line 649
• contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp, line 173
• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  • line 1699
  • line 1707
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  • line 2177
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  • line 2445
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  • line 4055
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• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  • line 822
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  • line 933
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• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, line 878
• contrib/llvm-project/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp, line 243
• contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
  • line 228
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  • line 653
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• contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  • line 743
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• contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
  • line 164
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• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp, line 1456
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyFixBrTableDefaults.cpp, line 91
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp, line 448
• contrib/llvm-project/llvm/lib/Target/X86/X86FloatingPoint.cpp
  • line 850
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• contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp
  • line 2073
  • line 2170
  • line 4077
  • line 4441
  • line 4548
  • line 4655
• contrib/llvm-project/llvm/lib/Target/X86/X86InstructionSelector.cpp
  • line 540
  • line 544
  • line 545
  • line 628
• contrib/llvm-project/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  • line 359
  • line 360