Defined in 31 files as a member:

• contrib/llvm/include/llvm/CodeGen/CalcSpillWeights.h, line 53 (as a member)
• contrib/llvm/include/llvm/CodeGen/LiveInterval.h, line 919 (as a member)
• contrib/llvm/include/llvm/CodeGen/LiveRangeEdit.h, line 74 (as a member)
• contrib/llvm/include/llvm/CodeGen/LiveRegMatrix.h, line 43 (as a member)
• contrib/llvm/include/llvm/CodeGen/MachineScheduler.h, line 125 (as a member)
• contrib/llvm/include/llvm/CodeGen/MachineScheduler.h, line 263 (as a member)
• contrib/llvm/include/llvm/CodeGen/RegAllocPBQP.h, line 144 (as a member)
• contrib/llvm/include/llvm/CodeGen/RegisterPressure.h, line 365 (as a member)
• contrib/llvm/lib/CodeGen/InlineSpiller.cpp, line 83 (as a member)
• contrib/llvm/lib/CodeGen/InlineSpiller.cpp, line 156 (as a member)
• contrib/llvm/lib/CodeGen/InterferenceCache.h, line 64 (as a member)
• contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp, line 329 (as a member)
• contrib/llvm/lib/CodeGen/LiveIntervals.cpp, line 917 (as a member)
• contrib/llvm/lib/CodeGen/MachinePipeliner.cpp, line 234 (as a member)
• contrib/llvm/lib/CodeGen/PHIElimination.cpp, line 69 (as a member)
• contrib/llvm/lib/CodeGen/RegAllocBase.h, line 68 (as a member)
• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 105 (as a member)
• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 1985 (as a member)
• contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp, line 104 (as a member)
• contrib/llvm/lib/CodeGen/SplitKit.h, line 51 (as a member)
• contrib/llvm/lib/CodeGen/SplitKit.h, line 87 (as a member)
• contrib/llvm/lib/CodeGen/SplitKit.h, line 244 (as a member)
• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 100 (as a member)
• contrib/llvm/lib/CodeGen/VirtRegMap.cpp, line 182 (as a member)
• contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.h, line 101 (as a member)
• contrib/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp, line 73 (as a member)
• contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, line 82 (as a member)
• contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 152 (as a member)
• contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, line 169 (as a member)
• contrib/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp, line 50 (as a member)
• contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp, line 67 (as a member)

Referenced in 70 files:

• contrib/llvm/include/llvm/CodeGen/CalcSpillWeights.h
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• contrib/llvm/include/llvm/CodeGen/LiveInterval.h, line 923
• contrib/llvm/include/llvm/CodeGen/LiveRangeEdit.h, line 140
• contrib/llvm/include/llvm/CodeGen/MachineScheduler.h
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• contrib/llvm/include/llvm/CodeGen/RegAllocPBQP.h
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• contrib/llvm/include/llvm/CodeGen/RegisterPressure.h
  • line 189
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• contrib/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h, line 308
• contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
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• contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 971
• contrib/llvm/lib/CodeGen/CalcSpillWeights.cpp
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• contrib/llvm/lib/CodeGen/InlineSpiller.cpp
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• contrib/llvm/lib/CodeGen/InterferenceCache.cpp
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• contrib/llvm/lib/CodeGen/InterferenceCache.h, line 109
• contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp
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• contrib/llvm/lib/CodeGen/LiveDebugVariables.h, line 53
• contrib/llvm/lib/CodeGen/LiveInterval.cpp
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• contrib/llvm/lib/CodeGen/LiveIntervals.cpp
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• contrib/llvm/lib/CodeGen/LiveRangeEdit.cpp
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• contrib/llvm/lib/CodeGen/LiveRegMatrix.cpp
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• contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
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• contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
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• contrib/llvm/lib/CodeGen/MachineScheduler.cpp
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• contrib/llvm/lib/CodeGen/PHIElimination.cpp
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• contrib/llvm/lib/CodeGen/RegAllocBase.cpp
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• contrib/llvm/lib/CodeGen/RegAllocBasic.cpp
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• contrib/llvm/lib/CodeGen/RegAllocGreedy.cpp
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• contrib/llvm/lib/CodeGen/RegAllocPBQP.cpp
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• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
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• contrib/llvm/lib/CodeGen/RegisterPressure.cpp
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• contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
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• contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
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• contrib/llvm/lib/CodeGen/SplitKit.cpp
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• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
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• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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• contrib/llvm/lib/CodeGen/VirtRegMap.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, line 2802
• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.h, line 277
• contrib/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
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• contrib/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
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• contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
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• contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.h
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• contrib/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp
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• contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIMachineScheduler.h
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• contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp, line 1495
• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h, line 217
• contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
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• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 808
• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h, line 210
• contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp, line 2237
• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, line 940
• contrib/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
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• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
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• contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
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• contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h, line 81
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
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• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
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• contrib/llvm/lib/Target/WebAssembly/WebAssemblyStoreResults.cpp
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• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
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• contrib/llvm/lib/Target/X86/X86InstrInfo.h
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