Defined in 2 files as a member:

• contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h, line 414 (as a member)
• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp, line 1968 (as a member)

Referenced in 53 files:

• contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 1126
• contrib/llvm/include/llvm/CodeGen/MachineOperand.h, line 425
• contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
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• contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
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• contrib/llvm/include/llvm/MC/MCRegisterInfo.h, line 357
• contrib/llvm/lib/CodeGen/DetectDeadLanes.cpp
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• contrib/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
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• contrib/llvm/lib/CodeGen/LiveDebugVariables.h, line 47
• contrib/llvm/lib/CodeGen/MachineCopyPropagation.cpp
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• contrib/llvm/lib/CodeGen/MachineInstr.cpp
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• contrib/llvm/lib/CodeGen/MachineOperand.cpp
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• contrib/llvm/lib/CodeGen/MachineVerifier.cpp
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• contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp
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• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
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• contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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• contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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• contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h, line 86
• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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• contrib/llvm/lib/CodeGen/SplitKit.cpp
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• contrib/llvm/lib/CodeGen/SplitKit.h, line 424
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
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• contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp
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• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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• contrib/llvm/lib/MC/MCRegisterInfo.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.h, line 54
• contrib/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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• contrib/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h, line 49
• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h, line 167
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
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• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
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• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h, line 185
• contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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• contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
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• contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.h, line 42
• contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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• contrib/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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• contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.h, line 203
• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
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• contrib/llvm/lib/Target/X86/X86InstrInfo.h
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• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp
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• contrib/llvm/lib/Target/X86/X86RegisterInfo.cpp
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• contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp
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• contrib/llvm/utils/TableGen/CodeGenRegisters.cpp
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• contrib/llvm/utils/TableGen/CodeGenRegisters.h
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• contrib/llvm/utils/TableGen/GlobalISelEmitter.cpp
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• contrib/llvm/utils/TableGen/RegisterBankEmitter.cpp
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