Defined in 2 files as a member:
- contrib/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 31 (as a member)
- contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp, line 292 (as a member)
Referenced in 54 files:
- contrib/llvm/include/llvm/CodeGen/MachineTraceMetrics.h, line 316
- contrib/llvm/include/llvm/CodeGen/RegisterScavenging.h
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 933
- contrib/llvm/include/llvm/CodeGen/TargetSchedule.h, line 172
- contrib/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
- contrib/llvm/lib/CodeGen/DetectDeadLanes.cpp
- contrib/llvm/lib/CodeGen/InlineSpiller.cpp
- contrib/llvm/lib/CodeGen/LiveIntervals.cpp
- contrib/llvm/lib/CodeGen/LiveRangeEdit.cpp
- contrib/llvm/lib/CodeGen/MachineLICM.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineRegisterInfo.cpp
- contrib/llvm/lib/CodeGen/MachineSSAUpdater.cpp
- contrib/llvm/lib/CodeGen/MachineTraceMetrics.cpp
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- contrib/llvm/lib/CodeGen/OptimizePHIs.cpp
- contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- contrib/llvm/lib/CodeGen/RegAllocFast.cpp
- contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm/lib/CodeGen/RegisterScavenging.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm/lib/CodeGen/TailDuplicator.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/CodeGen/TargetSchedule.cpp
- contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
- contrib/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
- contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
- contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.h, line 57
- contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h, line 306
- contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
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- contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
- contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.h, line 34
- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.h
- contrib/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
- contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
- contrib/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.h, line 220
- contrib/llvm/lib/Target/X86/X86DomainReassignment.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp, line 10207
- contrib/llvm/lib/Target/X86/X86InstrInfo.h, line 521