Defined in 2 files as a member:
- contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 87 (as a member)
- contrib/llvm/lib/Transforms/Utils/ValueMapper.cpp, line 87 (as a member)
Referenced in 54 files:
- contrib/llvm/include/llvm/CodeGen/MachineFunction.h, line 629
- contrib/llvm/include/llvm/CodeGen/MachineInstr.h
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- contrib/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
- contrib/llvm/include/llvm/MC/MCInstrDesc.h
- contrib/llvm/lib/CodeGen/ExecutionDepsFix.cpp
- contrib/llvm/lib/CodeGen/MIRParser/MIParser.cpp
- contrib/llvm/lib/CodeGen/MachineFunction.cpp
- contrib/llvm/lib/CodeGen/MachineInstr.cpp
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- contrib/llvm/lib/CodeGen/RegAllocFast.cpp
- contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
- contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
- contrib/llvm/lib/Target/ARM/ARMFastISel.cpp
- contrib/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
- contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
- contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
- contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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- contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp
- contrib/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
- contrib/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
- contrib/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp
- contrib/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
- contrib/llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
- contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
- contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.h, line 33
- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- contrib/llvm/lib/Target/X86/X86InstrBuilder.h
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm/lib/Transforms/Utils/ValueMapper.cpp