Defined in 1 files as a prototype:

• contrib/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 671 (as a prototype)

Defined in 1 files as a function:

• contrib/llvm/lib/CodeGen/MachineRegisterInfo.cpp, line 121 (as a function)

Referenced in 122 files:

• contrib/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h, line 70
• contrib/llvm/lib/CodeGen/EarlyIfConversion.cpp, line 491
• contrib/llvm/lib/CodeGen/GlobalISel/Utils.cpp, line 35
• contrib/llvm/lib/CodeGen/LiveIntervals.cpp, line 1587
• contrib/llvm/lib/CodeGen/LiveRangeEdit.cpp, 2 times
• contrib/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp, line 406
• contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp, 7 times
• contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp, line 428
• contrib/llvm/lib/CodeGen/MachineFunction.cpp, line 608
• contrib/llvm/lib/CodeGen/MachineLICM.cpp, line 1197
• contrib/llvm/lib/CodeGen/MachinePipeliner.cpp, 4 times
• contrib/llvm/lib/CodeGen/MachineSSAUpdater.cpp, line 122
• contrib/llvm/lib/CodeGen/PHIElimination.cpp, line 276
• contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp, 3 times
• contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp, line 142
• contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp, line 1796
• contrib/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp, 4 times
• contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp, 10 times
• contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp, line 783
• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp, 3 times
• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp, 2 times
• contrib/llvm/lib/CodeGen/TailDuplicator.cpp, 3 times
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 817
• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 1350
• contrib/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp, 3 times
• contrib/llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp, line 123
• contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp, line 631
• contrib/llvm/lib/Target/AArch64/AArch64FastISel.cpp, 6 times
• contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp, line 10936
• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, 6 times
• contrib/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp, 11 times
• contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 401
• contrib/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp, 3 times
• contrib/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp, line 3804
• contrib/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp, 6 times
• contrib/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp, 12 times
• contrib/llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp, 2 times
• contrib/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp, line 215
• contrib/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp, line 298
• contrib/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp, line 717
• contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, 20 times
• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, 63 times
• contrib/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp, 6 times
• contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, 4 times
• contrib/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp, line 124
• contrib/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 1038
• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp, 11 times
• contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, 4 times
• contrib/llvm/lib/Target/ARC/ARCExpandPseudos.cpp, line 63
• contrib/llvm/lib/Target/ARC/ARCISelLowering.cpp, 2 times
• contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp, 6 times
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, line 2993
• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 788
• contrib/llvm/lib/Target/ARM/ARMFastISel.cpp, line 2973
• contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp, 2 times
• contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp, 51 times
• contrib/llvm/lib/Target/ARM/ARMInstructionSelector.cpp, 5 times
• contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp, line 290
• contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, 2 times
• contrib/llvm/lib/Target/AVR/AVRFrameLowering.cpp, line 515
• contrib/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp, 2 times
• contrib/llvm/lib/Target/AVR/AVRISelLowering.cpp, 4 times
• contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp, line 205
• contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp, 16 times
• contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp, line 1428
• contrib/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp, 6 times
• contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, 2 times
• contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, 7 times
• contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp, line 1386
• contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp, 3 times
• contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp, 8 times
• contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp, 9 times
• contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp, line 1826
• contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp, line 221
• contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, 7 times
• contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 446
• contrib/llvm/lib/Target/Lanai/LanaiISelLowering.cpp, 2 times
• contrib/llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.cpp, line 22
• contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp, 6 times
• contrib/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp, 3 times
• contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp, 43 times
• contrib/llvm/lib/Target/Mips/MipsMachineFunction.cpp, line 50
• contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp, 9 times
• contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp, 2 times
• contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp, 37 times
• contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp, line 517
• contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp, line 227
• contrib/llvm/lib/Target/Nios2/Nios2ISelLowering.cpp, line 46
• contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp, 5 times
• contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp, 43 times
• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp, line 859
• contrib/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp, 2 times
• contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, 17 times
• contrib/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp, 2 times
• contrib/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp, 3 times
• contrib/llvm/lib/Target/RISCV/RISCVISelLowering.cpp, line 526
• contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp, 2 times
• contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp, 9 times
• contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp, line 486
• contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp, 40 times
• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp, 2 times
• contrib/llvm/lib/Target/SystemZ/SystemZLDCleanup.cpp, line 136
• contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp, line 205
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp, 3 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp, line 193
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp, 8 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp, 10 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp, line 116
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, 4 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp, line 89
• contrib/llvm/lib/Target/X86/X86CallFrameOptimization.cpp, 2 times
• contrib/llvm/lib/Target/X86/X86CmovConversion.cpp, line 765
• contrib/llvm/lib/Target/X86/X86DomainReassignment.cpp, line 189
• contrib/llvm/lib/Target/X86/X86FixupSetCC.cpp, 2 times
• contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp, 2 times
• contrib/llvm/lib/Target/X86/X86FrameLowering.cpp, 9 times
• contrib/llvm/lib/Target/X86/X86ISelLowering.cpp, 33 times
• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp, 9 times
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, 3 times
• contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp, 2 times