Defined in 2 files as a member:

• contrib/binutils/opcodes/arc-dis.h, line 74 (as a member)
• contrib/llvm/utils/TableGen/CodeGenInstruction.h, line 225 (as a member)

Defined in 5 files as a function:

• contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 485 (as a function)
• contrib/llvm/include/llvm/MC/MCInstrAnalysis.h, line 35 (as a function)
• contrib/llvm/include/llvm/MC/MCInstrDesc.h, line 270 (as a function)
• contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp, line 664 (as a function)
• contrib/llvm/tools/lld/ELF/AArch64ErrataFix.cpp, line 237 (as a function)

Referenced in 61 files:

• contrib/binutils/opcodes/arc-dis.c
  • line 550
  • line 756
• contrib/llvm/include/llvm/CodeGen/MachineInstr.h
  • line 500
  • line 508
• contrib/llvm/include/llvm/MC/MCInstrAnalysis.h, line 36
• contrib/llvm/include/llvm/MC/MCInstrDesc.h
  • line 281
  • line 289
• contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp, line 2761
• contrib/llvm/lib/CodeGen/BranchFolding.cpp
  • line 1287
  • line 1317
• contrib/llvm/lib/CodeGen/IfConversion.cpp
  • line 649
  • line 688
  • line 739
  • line 743
  • line 747
  • line 747
  • line 990
  • line 1774
  • line 2032
• contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
  • line 253
  • line 539
  • line 554
• contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
  • line 1198
  • line 1204
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 291
• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 893
  • line 950
  • line 1124
• contrib/llvm/lib/MC/MCInstrDesc.cpp, line 35
• contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp, line 683
• contrib/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp, line 1161
• contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, line 132
• contrib/llvm/lib/Target/ARC/ARCBranchFinalize.cpp, line 163
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, line 3972
• contrib/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
  • line 675
  • line 708
• contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 540
• contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 8887
• contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  • line 527
  • line 531
• contrib/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp, line 239
• contrib/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp, line 63
• contrib/llvm/lib/Target/AVR/AVRInstrInfo.cpp, line 288
• contrib/llvm/lib/Target/BPF/BPFInstrInfo.cpp, line 96
• contrib/llvm/lib/Target/Hexagon/BitTracker.cpp
  • line 845
  • line 928
  • line 1030
  • line 1077
  • line 1108
• contrib/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
  • line 176
  • line 194
• contrib/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  • line 791
  • line 804
  • line 907
  • line 984
  • line 1034
  • line 2318
• contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, line 679
• contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  • line 532
  • line 1361
  • line 1844
  • line 1849
  • line 2239
  • line 2243
  • line 2302
  • line 2408
  • line 3398
  • line 4165
• contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  • line 1107
  • line 1246
  • line 1479
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
  • line 545
  • line 547
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
  • line 305
  • line 316
  • line 330
  • line 417
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
  • line 221
  • line 232
  • line 651
  • line 669
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
  • line 525
  • line 527
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
  • line 386
  • line 393
  • line 395
• contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 59
• contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp
  • line 241
  • line 641
  • line 1274
• contrib/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 587
• contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  • line 169
  • line 196
• contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 1788
• contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp, line 667
• contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
  • line 356
  • line 687
• contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp, line 451
• contrib/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
  • line 251
  • line 687
• contrib/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp, line 122
• contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
  • line 61
  • line 179
  • line 200
• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  • line 177
  • line 1402
• contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
  • line 511
  • line 516
• contrib/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
  • line 74
  • line 79
  • line 250
  • line 255
• contrib/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp, line 208
• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  • line 402
  • line 484
• contrib/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp, line 106
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp, line 72
• contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  • line 294
  • line 298
  • line 384
  • line 387
  • line 671
• contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  • line 247
  • line 254
• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
  • line 6068
  • line 6130
  • line 6206
  • line 7377
  • line 7426
• contrib/llvm/tools/lld/ELF/AArch64ErrataFix.cpp, line 367
• contrib/llvm/utils/TableGen/CodeGenInstruction.cpp, line 305
• contrib/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 103
• contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 486