Defined in 2 files as a member:
Defined in 3 files as a function:
Referenced in 63 files:
- contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 653
- contrib/llvm/include/llvm/CodeGen/ScheduleDAG.h, line 392
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/lib/CodeGen/BranchFolding.cpp
- contrib/llvm/lib/CodeGen/EarlyIfConversion.cpp, line 216
- contrib/llvm/lib/CodeGen/ImplicitNullChecks.cpp
- contrib/llvm/lib/CodeGen/MachineCSE.cpp, line 369
- contrib/llvm/lib/CodeGen/MachineInstr.cpp
- contrib/llvm/lib/CodeGen/MachineLICM.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineScheduler.cpp, line 1600
- contrib/llvm/lib/CodeGen/MachineSink.cpp, line 742
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp, line 1312
- contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp, line 299
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm/lib/CodeGen/StackColoring.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/CodeGen/TargetLoweringBase.cpp, line 958
- contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 1334
- contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp, line 413
- contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 267
- contrib/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp, line 570
- contrib/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2070
- contrib/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp, line 44
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, line 580
- contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, line 677
- contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, line 2219
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 274
- contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
- contrib/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp, line 187
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
- contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp, line 289
- contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
- contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp, line 238
- contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h, line 33
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 166
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp, line 74
- contrib/llvm/lib/Target/X86/X86CmovConversion.cpp
- contrib/llvm/lib/Target/X86/X86InstrBuilder.h, line 205
- contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
- contrib/llvm/utils/TableGen/CodeGenInstruction.cpp, line 332
- contrib/llvm/utils/TableGen/DAGISelMatcherGen.cpp
- contrib/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 2149
- contrib/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 113
- contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 497