Defined in 2 files as a member:

• contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp, line 3216 (as a member)
• contrib/llvm/utils/TableGen/CodeGenInstruction.h, line 237 (as a member)

Defined in 3 files as a function:

• contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 642 (as a function)
• contrib/llvm/include/llvm/MC/MCInstrDesc.h, line 393 (as a function)
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h, line 101 (as a function)

Referenced in 77 files:

• contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 653
• contrib/llvm/include/llvm/CodeGen/ScheduleDAG.h, line 392
• contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
  • line 1496
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• contrib/llvm/lib/CodeGen/BranchFolding.cpp
  • line 461
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• contrib/llvm/lib/CodeGen/ImplicitNullChecks.cpp
  • line 325
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• contrib/llvm/lib/CodeGen/InlineSpiller.cpp, line 447
• contrib/llvm/lib/CodeGen/LiveRangeShrink.cpp, line 135
• contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
  • line 253
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  • line 554
• contrib/llvm/lib/CodeGen/MachineCSE.cpp, line 365
• contrib/llvm/lib/CodeGen/MachineInstr.cpp
  • line 938
  • line 969
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  • line 1052
  • line 1140
• contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
  • line 1044
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• contrib/llvm/lib/CodeGen/MachineScheduler.cpp, line 1601
• contrib/llvm/lib/CodeGen/MachineVerifier.cpp
  • line 892
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• contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  • line 861
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• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  • line 3625
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• contrib/llvm/lib/CodeGen/StackColoring.cpp
  • line 999
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• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
  • line 576
  • line 898
• contrib/llvm/lib/MC/MCParser/AsmParser.cpp, line 5543
• contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  • line 1043
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  • line 1095
  • line 1115
• contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 267
• contrib/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp, line 570
• contrib/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  • line 347
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• contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, line 7005
• contrib/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  • line 493
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• contrib/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp
  • line 205
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• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 288
  • line 2094
  • line 2096
  • line 2834
  • line 4579
• contrib/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  • line 189
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• contrib/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
  • line 265
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• contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, line 142
• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  • line 491
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• contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 426
• contrib/llvm/lib/Target/ARM/ARMAsmPrinter.cpp, line 1079
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
  • line 172
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• contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
  • line 1287
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  • line 1297
• contrib/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp, line 24
• contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp, line 410
• contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2070
• contrib/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp, line 45
• contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp, line 189
• contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, line 604
• contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
  • line 631
  • line 2589
• contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
  • line 842
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• contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
  • line 672
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• contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
  • line 712
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• contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, line 2218
• contrib/llvm/lib/Target/Hexagon/HexagonGatherPacketize.cpp, line 57
• contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  • line 1841
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• contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp, line 186
• contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
  • line 120
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  • line 186
  • line 192
  • line 289
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  • line 517
• contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, line 161
• contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 274
• contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
  • line 163
  • line 173
  • line 269
  • line 282
• contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  • line 354
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• contrib/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp
  • line 117
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• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 467
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
  • line 288
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• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
  • line 155
  • line 269
  • line 378
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• contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 59
• contrib/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp, line 193
• contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 2096
• contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
  • line 42
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• contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp, line 244
• contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h, line 35
• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp, line 95
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 170
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp, line 75
• contrib/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp, line 425
• contrib/llvm/lib/Target/X86/X86CallFrameOptimization.cpp, line 335
• contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  • line 611
  • line 917
• contrib/llvm/lib/Target/X86/X86InstrBuilder.h, line 207
• contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
  • line 3222
  • line 3236
  • line 3266
  • line 3285
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• contrib/llvm/utils/TableGen/CodeGenInstruction.cpp, line 334
• contrib/llvm/utils/TableGen/DAGISelMatcherGen.cpp
  • line 695
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• contrib/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 2149
• contrib/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 115
• contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 498