Defined in 2 files as a member:
- contrib/llvm/tools/clang/lib/ARCMigrate/TransformActions.cpp, line 47 (as a member)
- sys/contrib/edk2/Include/Library/BaseLib.h, line 119 (as a member)
Defined in 8 files as a macro:
- contrib/binutils/opcodes/ia64-opc.h, line 70 (as a macro)
- contrib/ldns/sha1.c, line 39 (as a macro)
- contrib/ntp/lib/isc/sha1.c, line 110 (as a macro)
- contrib/wpa/src/crypto/sha1-internal.c, line 147 (as a macro)
- crypto/openssh/openbsd-compat/sha1.c, line 43 (as a macro)
- crypto/openssl/crypto/md4/md4_locl.h, line 54 (as a macro)
- crypto/openssl/crypto/md5/md5_locl.h, line 67 (as a macro)
- crypto/openssl/crypto/sm3/sm3_locl.h, line 66 (as a macro)
Referenced in 77 files:
- contrib/binutils/opcodes/ia64-opc-a.c
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- contrib/binutils/opcodes/ia64-opc-i.c
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- contrib/binutils/opcodes/ia64-opc-m.c
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- contrib/binutils/opcodes/ia64-opc-x.c, line 68
- contrib/gcc/config/ia64/unwind-ia64.c, line 1156
- contrib/gcc/conflict.c
- contrib/gdb/gdb/dpx2-nat.c, line 39
- contrib/gdb/gdb/wince.c
- contrib/ldns/sha1.c
- contrib/llvm/include/llvm/MC/MCDwarf.h
- contrib/llvm/lib/Analysis/ScalarEvolution.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
- contrib/llvm/lib/Target/ARC/ARCISelLowering.cpp, line 522
- contrib/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp, line 115
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h, line 48
- contrib/llvm/lib/Target/ARM/ARMCallingConv.h
- contrib/llvm/lib/Target/ARM/ARMFastISel.cpp, line 3056
- contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
- contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
- contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
- contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
- contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h, line 150
- contrib/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
- contrib/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp, line 505
- contrib/llvm/lib/Target/AVR/AVRISelLowering.cpp
- contrib/llvm/lib/Target/AVR/AVRRegisterInfo.cpp, line 58
- contrib/llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp, line 68
- contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
- contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
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- contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.h, line 205
- contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp, line 669
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp, line 257
- contrib/llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp, line 154
- contrib/llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
- contrib/llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp, line 45
- contrib/llvm/lib/Target/Lanai/MCTargetDesc/LanaiBaseInfo.h, line 45
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- contrib/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
- contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
- contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp, line 89
- contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
- contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
- contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
- contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
- contrib/llvm/lib/Target/XCore/XCoreISelLowering.cpp, line 1345
- contrib/llvm/lib/Target/XCore/XCoreISelLowering.h, line 140
- contrib/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
- contrib/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
- contrib/llvm/tools/clang/include/clang/AST/Expr.h, line 233
- contrib/llvm/tools/clang/include/clang/Analysis/Analyses/ReachableCode.h, line 55
- contrib/llvm/tools/clang/lib/ARCMigrate/TransformActions.cpp
- contrib/llvm/tools/clang/lib/AST/Expr.cpp
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- contrib/llvm/tools/clang/lib/AST/RawCommentList.cpp
- contrib/llvm/tools/clang/lib/Analysis/CFG.cpp
- contrib/llvm/tools/clang/lib/Analysis/ReachableCode.cpp
- contrib/llvm/tools/clang/lib/Sema/AnalysisBasedWarnings.cpp
- contrib/llvm/tools/clang/lib/Sema/SemaStmt.cpp
- contrib/llvm/tools/clang/lib/Tooling/Core/Replacement.cpp
- contrib/llvm/tools/clang/utils/TableGen/NeonEmitter.cpp
- contrib/llvm/tools/lld/COFF/ICF.cpp
- contrib/llvm/utils/TableGen/CodeGenRegisters.h
- contrib/ntp/lib/isc/sha1.c
- contrib/wpa/src/crypto/sha1-internal.c
- crypto/openssh/openbsd-compat/sha1.c
- crypto/openssl/crypto/md4/md4_dgst.c
- crypto/openssl/crypto/md5/md5_dgst.c
- crypto/openssl/crypto/sm3/sm3.c
- secure/lib/libcrypto/arm/poly1305-armv4.S, line 487
- sys/cddl/dev/dtrace/arm/regset.h, line 50