Defined in 6 files as a member:
- contrib/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h, line 65 (as a member)
- contrib/llvm/lib/CodeGen/CodeGenPrepare.cpp, line 1929 (as a member)
- contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp, line 217 (as a member)
- contrib/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp, line 129 (as a member)
- contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 337 (as a member)
- contrib/llvm/lib/Target/X86/AsmParser/X86Operand.h, line 61 (as a member)
Referenced in 61 files:
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
- contrib/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
- contrib/llvm/lib/CodeGen/CodeGenPrepare.cpp
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- contrib/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
- contrib/llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/MC/MCParser/AsmParser.cpp, line 5778
- contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
- contrib/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
- contrib/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
- contrib/llvm/lib/Target/ARC/ARCRegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
- contrib/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
- contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
- contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
- contrib/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
- contrib/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.h, line 53
- contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
- contrib/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
- contrib/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp
- contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
- contrib/llvm/lib/Target/Mips/MipsTargetStreamer.h
- contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
- contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
- contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
- contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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- contrib/llvm/lib/Target/X86/AsmParser/X86Operand.h
- contrib/llvm/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
- contrib/llvm/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
- contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
- contrib/llvm/lib/Target/X86/X86AsmPrinter.cpp
- contrib/llvm/lib/Target/X86/X86InsertPrefetch.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm/lib/Target/X86/X86MCInstLower.cpp
- contrib/llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
- contrib/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
- contrib/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
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- contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp
- contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/RegionStore.cpp
- contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/Store.cpp