Defined in 2 files as a member:
- contrib/llvm/include/llvm/CodeGen/MachineFrameInfo.h, line 37 (as a member)
- contrib/llvm/lib/CodeGen/RegisterCoalescer.h, line 32 (as a member)
Referenced in 97 files:
- contrib/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h, line 215
- contrib/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
- contrib/llvm/include/llvm/CodeGen/MachineFrameInfo.h
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/lib/CodeGen/EarlyIfConversion.cpp
- contrib/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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- contrib/llvm/lib/CodeGen/InlineSpiller.cpp
- contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp
- contrib/llvm/lib/CodeGen/MachineScheduler.cpp
- contrib/llvm/lib/CodeGen/MachineSink.cpp
- contrib/llvm/lib/CodeGen/OptimizePHIs.cpp
- contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- contrib/llvm/lib/CodeGen/PrologEpilogInserter.cpp
- contrib/llvm/lib/CodeGen/RegAllocPBQP.cpp
- contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
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- contrib/llvm/lib/CodeGen/RegisterCoalescer.h
- contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
- contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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- contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
- contrib/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
- contrib/llvm/lib/Target/AArch64/AArch64FastISel.cpp
- contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.h
- contrib/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
- contrib/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h, line 31
- contrib/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
- contrib/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
- contrib/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
- contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.h
- contrib/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h
- contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
- contrib/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
- contrib/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
- contrib/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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- contrib/llvm/lib/Target/ARM/ARMFastISel.cpp
- contrib/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
- contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp
- contrib/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
- contrib/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
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- contrib/llvm/lib/Target/AVR/AVRISelLowering.cpp
- contrib/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
- contrib/llvm/lib/Target/BPF/BPFInstrInfo.cpp
- contrib/llvm/lib/Target/BPF/BPFMIPeephole.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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- contrib/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
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- contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
- contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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- contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
- contrib/llvm/lib/Target/Mips/MipsFastISel.cpp
- contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp
- contrib/llvm/lib/Target/Mips/MipsISelLowering.h, line 689
- contrib/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
- contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
- contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
- contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
- contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
- contrib/llvm/lib/Target/Mips/MipsTargetStreamer.h
- contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
- contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.h
- contrib/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
- contrib/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
- contrib/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
- contrib/llvm/lib/Target/RISCV/RISCVInstrInfo.h
- contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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- contrib/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp
- contrib/llvm/lib/Target/X86/X86DomainReassignment.cpp
- contrib/llvm/lib/Target/X86/X86FastISel.cpp
- contrib/llvm/lib/Target/X86/X86FixupLEAs.cpp
- contrib/llvm/lib/Target/X86/X86FloatingPoint.cpp
- contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.h
- contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp
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