Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 73 files:
- contrib/llvm/include/llvm/CodeGen/CalcSpillWeights.h
- contrib/llvm/include/llvm/CodeGen/LiveInterval.h
- contrib/llvm/include/llvm/CodeGen/LiveIntervals.h
- contrib/llvm/include/llvm/CodeGen/LiveRangeEdit.h
- contrib/llvm/include/llvm/CodeGen/LiveRegMatrix.h
- contrib/llvm/include/llvm/CodeGen/MachinePipeliner.h
- contrib/llvm/include/llvm/CodeGen/MachineScheduler.h
- contrib/llvm/include/llvm/CodeGen/RegAllocPBQP.h
- contrib/llvm/include/llvm/CodeGen/RegisterPressure.h
- contrib/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
- contrib/llvm/lib/CodeGen/CalcSpillWeights.cpp
- contrib/llvm/lib/CodeGen/InlineSpiller.cpp
- contrib/llvm/lib/CodeGen/InterferenceCache.cpp, line 58
- contrib/llvm/lib/CodeGen/InterferenceCache.h
- contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp
- contrib/llvm/lib/CodeGen/LiveDebugVariables.h
- contrib/llvm/lib/CodeGen/LiveIntervals.cpp
- contrib/llvm/lib/CodeGen/LiveRegMatrix.cpp
- contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineScheduler.cpp
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/PHIElimination.cpp
- contrib/llvm/lib/CodeGen/RegAllocBase.cpp, line 58
- contrib/llvm/lib/CodeGen/RegAllocBase.h
- contrib/llvm/lib/CodeGen/RegAllocBasic.cpp
- contrib/llvm/lib/CodeGen/RegAllocGreedy.cpp
- contrib/llvm/lib/CodeGen/RegAllocPBQP.cpp
- contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm/lib/CodeGen/RegisterPressure.cpp
- contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
- contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp, line 707
- contrib/llvm/lib/CodeGen/SplitKit.cpp
- contrib/llvm/lib/CodeGen/SplitKit.h
- contrib/llvm/lib/CodeGen/StackSlotColoring.cpp, line 177
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
- contrib/llvm/lib/CodeGen/VirtRegMap.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, line 2963
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.h, line 153
- contrib/llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.h
- contrib/llvm/lib/Target/AMDGPU/SIFixWWMLiveness.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
- contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
- contrib/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
- contrib/llvm/lib/Target/AMDGPU/SIMachineScheduler.h, line 459
- contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp, line 51
- contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
- contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 813
- contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
- contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp, line 239
- contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h, line 66
- contrib/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
- contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
- contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp, line 266
- contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm/lib/Target/X86/X86InstrInfo.h