RegState identifier - Freebsd-lockdoc source code (lockdoc-v12.0-0.3)

Defined in 1 files as a enum:

contrib/llvm/lib/CodeGen/RegAllocFast.cpp, line 106 (as a enum)

Referenced in 100 files:

contrib/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
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contrib/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
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contrib/llvm/lib/CodeGen/IfConversion.cpp
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contrib/llvm/lib/CodeGen/MIRParser/MIParser.cpp
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contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp, line 509
contrib/llvm/lib/CodeGen/MachineInstr.cpp
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contrib/llvm/lib/CodeGen/RegAllocFast.cpp
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contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
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contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp, line 1188
contrib/llvm/lib/CodeGen/SplitKit.cpp, line 519
contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 1841
contrib/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
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contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
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contrib/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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contrib/llvm/lib/Target/AArch64/AArch64FastISel.cpp
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contrib/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
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contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp, line 855
contrib/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
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contrib/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp, line 1771
contrib/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
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contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
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contrib/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp, line 169
contrib/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 228
contrib/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
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contrib/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
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contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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contrib/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
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contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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contrib/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
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contrib/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
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contrib/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
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contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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contrib/llvm/lib/Target/ARC/ARCFrameLowering.cpp
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contrib/llvm/lib/Target/ARC/ARCInstrInfo.cpp, line 331
contrib/llvm/lib/Target/ARC/ARCRegisterInfo.cpp
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contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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contrib/llvm/lib/Target/ARM/ARMCallLowering.cpp
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contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
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contrib/llvm/lib/Target/ARM/ARMFastISel.cpp
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contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
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contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
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contrib/llvm/lib/Target/ARM/ARMInstrInfo.cpp, line 133
contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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contrib/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp
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contrib/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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contrib/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
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contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
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contrib/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
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contrib/llvm/lib/Target/AVR/AVRFrameLowering.cpp
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contrib/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
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contrib/llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp, line 105
contrib/llvm/lib/Target/BPF/BPFISelLowering.cpp
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contrib/llvm/lib/Target/BPF/BPFInstrInfo.cpp
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contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
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contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
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contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
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contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 463
contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp
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contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
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contrib/llvm/lib/Target/Mips/MipsCallLowering.cpp
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contrib/llvm/lib/Target/Mips/MipsExpandPseudo.cpp
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contrib/llvm/lib/Target/Mips/MipsFastISel.cpp
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contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp
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contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
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contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
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contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
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contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp, line 251
contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp
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contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
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contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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contrib/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp, line 81
contrib/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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contrib/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp, line 101
contrib/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
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contrib/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
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contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
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contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp, line 248
contrib/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp
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contrib/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp, line 853
contrib/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp, line 79
contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 604
contrib/llvm/lib/Target/X86/ShadowCallStack.cpp
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contrib/llvm/lib/Target/X86/X86CallLowering.cpp
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contrib/llvm/lib/Target/X86/X86ExpandPseudo.cpp
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contrib/llvm/lib/Target/X86/X86FastISel.cpp
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contrib/llvm/lib/Target/X86/X86FixupBWInsts.cpp
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contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp, line 829
contrib/llvm/lib/Target/X86/X86FrameLowering.cpp
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contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
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contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
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contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp
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contrib/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
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contrib/llvm/lib/Target/X86/X86WinAllocaExpander.cpp
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contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp, line 291
contrib/llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
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