Defined in 2 files as a prototype:

• contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h, line 143 (as a prototype)
• contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h, line 145 (as a prototype)

Defined in 2 files as a function:

• contrib/llvm/lib/CodeGen/TargetPassConfig.cpp, line 392 (as a function)
• contrib/llvm/lib/CodeGen/TargetPassConfig.cpp, line 448 (as a function)

Referenced in 82 files:

• contrib/llvm/include/llvm/CodeGen/GlobalISel/Combiner.h
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• contrib/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h
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• contrib/llvm/include/llvm/CodeGen/GlobalISel/RegBankSelect.h
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• contrib/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
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• contrib/llvm/include/llvm/CodeGen/MachineScheduler.h
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• contrib/llvm/include/llvm/CodeGen/TargetPassConfig.h, line 147
• contrib/llvm/include/llvm/Target/TargetMachine.h
  • line 44
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• contrib/llvm/lib/CodeGen/AtomicExpandPass.cpp, line 199
• contrib/llvm/lib/CodeGen/BranchFolding.cpp
  • line 106
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• contrib/llvm/lib/CodeGen/CodeGenPrepare.cpp, line 405
• contrib/llvm/lib/CodeGen/DwarfEHPrepare.cpp
  • line 87
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• contrib/llvm/lib/CodeGen/ExpandMemCmp.cpp, line 785
• contrib/llvm/lib/CodeGen/GlobalISel/Combiner.cpp, line 82
• contrib/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
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• contrib/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
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• contrib/llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
  • line 47
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• contrib/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
  • line 68
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• contrib/llvm/lib/CodeGen/GlobalISel/Utils.cpp
  • line 156
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• contrib/llvm/lib/CodeGen/IndirectBrExpandPass.cpp, line 78
• contrib/llvm/lib/CodeGen/InterleavedAccessPass.cpp, line 440
• contrib/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp, line 1318
• contrib/llvm/lib/CodeGen/LLVMTargetMachine.cpp
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• contrib/llvm/lib/CodeGen/LowerEmuTLS.cpp, line 66
• contrib/llvm/lib/CodeGen/MachineBlockPlacement.cpp
  • line 527
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• contrib/llvm/lib/CodeGen/MachineScheduler.cpp
  • line 217
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• contrib/llvm/lib/CodeGen/PostRASchedulerList.cpp
  • line 91
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• contrib/llvm/lib/CodeGen/SafeStack.cpp
  • line 856
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• contrib/llvm/lib/CodeGen/StackProtector.cpp
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• contrib/llvm/lib/CodeGen/TargetPassConfig.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
  • line 93
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• contrib/llvm/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
  • line 74
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• contrib/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
  • line 336
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• contrib/llvm/lib/Target/AArch64/AArch64TargetMachine.h, line 45
• contrib/llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp, line 312
• contrib/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
  • line 73
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• contrib/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp, line 893
• contrib/llvm/lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp, line 115
• contrib/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
  • line 55
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• contrib/llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp, line 369
• contrib/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp, line 150
• contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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• contrib/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
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• contrib/llvm/lib/Target/ARC/ARCTargetMachine.cpp
  • line 51
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• contrib/llvm/lib/Target/ARC/ARCTargetMachine.h
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• contrib/llvm/lib/Target/ARM/ARMCodeGenPrepare.cpp
  • line 163
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• contrib/llvm/lib/Target/ARM/ARMParallelDSP.cpp
  • line 157
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• contrib/llvm/lib/Target/ARM/ARMTargetMachine.cpp
  • line 307
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• contrib/llvm/lib/Target/ARM/ARMTargetMachine.h, line 59
• contrib/llvm/lib/Target/AVR/AVRTargetMachine.cpp
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• contrib/llvm/lib/Target/AVR/AVRTargetMachine.h, line 44
• contrib/llvm/lib/Target/BPF/BPFTargetMachine.cpp
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• contrib/llvm/lib/Target/BPF/BPFTargetMachine.h, line 36
• contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
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• contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.h, line 41
• contrib/llvm/lib/Target/Lanai/LanaiTargetMachine.cpp
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• contrib/llvm/lib/Target/Lanai/LanaiTargetMachine.h, line 48
• contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp
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• contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.h, line 40
• contrib/llvm/lib/Target/Mips/Mips16HardFloat.cpp
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• contrib/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp
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• contrib/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp
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• contrib/llvm/lib/Target/Mips/MipsTargetMachine.cpp
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• contrib/llvm/lib/Target/Mips/MipsTargetMachine.h, line 61
• contrib/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp
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• contrib/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h, line 56
• contrib/llvm/lib/Target/PowerPC/PPCBoolRetToInt.cpp, line 192
• contrib/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp, line 190
• contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
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• contrib/llvm/lib/Target/PowerPC/PPCTargetMachine.h, line 50
• contrib/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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• contrib/llvm/lib/Target/RISCV/RISCVTargetMachine.h, line 38
• contrib/llvm/lib/Target/Sparc/SparcTargetMachine.cpp
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• contrib/llvm/lib/Target/Sparc/SparcTargetMachine.h, line 39
• contrib/llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
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• contrib/llvm/lib/Target/SystemZ/SystemZTargetMachine.h, line 46
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
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• contrib/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h, line 40
• contrib/llvm/lib/Target/X86/X86TargetMachine.cpp
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• contrib/llvm/lib/Target/X86/X86TargetMachine.h, line 51
• contrib/llvm/lib/Target/XCore/XCoreTargetMachine.cpp
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• contrib/llvm/lib/Target/XCore/XCoreTargetMachine.h, line 44
• contrib/llvm/tools/llc/llc.cpp
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