Defined in 1 files as a function:

• contrib/llvm/include/llvm/MC/MCRegisterInfo.h, line 443 (as a function)

Referenced in 53 files:

• contrib/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp, line 715
• contrib/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp, line 343
• contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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• contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.h, line 35
• contrib/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
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• contrib/llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp
  • line 101
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• contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp, line 205
• contrib/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp, line 61
• contrib/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp, line 319
• contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
  • line 168
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• contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  • line 340
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• contrib/llvm/lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp
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• contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
  • line 353
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• contrib/llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
  • line 76
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• contrib/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  • line 466
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• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h, line 124
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 331
• contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
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• contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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• contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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• contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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• contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp
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• contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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• contrib/llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp, line 254
• contrib/llvm/lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp
  • line 91
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• contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
  • line 1338
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• contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp, line 463
• contrib/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
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• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp, line 790
• contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp
  • line 107
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• contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
  • line 99
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• contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp, line 82
• contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
  • line 1093
  • line 1095
• contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp, line 341
• contrib/llvm/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp, line 512
• contrib/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  • line 221
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  • line 275
• contrib/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp, line 1059
• contrib/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
  • line 347
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• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp, line 929
• contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  • line 602
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• contrib/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp, line 166
• contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp, line 128
• contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp, line 176
• contrib/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
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• contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
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• contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp, line 75
• contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
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• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
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• contrib/llvm/lib/Target/X86/X86RegisterInfo.cpp, line 84
• contrib/llvm/tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
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• contrib/llvm/tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
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