Defined in 5 files as a prototype:

• contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h, line 84 (as a prototype)
• contrib/llvm/lib/CodeGen/MIRParser/MIRParser.cpp, line 160 (as a prototype)
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, line 131 (as a prototype)
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, line 132 (as a prototype)
• contrib/llvm/utils/TableGen/CodeGenRegisters.h, line 703 (as a prototype)

Defined in 10 files as a function:

• contrib/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h, line 104 (as a function)
• contrib/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 627 (as a function)
• contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 696 (as a function)
• contrib/llvm/include/llvm/MC/MCRegisterInfo.h, line 433 (as a function)
• contrib/llvm/lib/CodeGen/MIRParser/MIRParser.cpp, line 873 (as a function)
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 45 (as a function)
• contrib/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 1559 (as a function)
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, line 173 (as a function)
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, line 201 (as a function)
• contrib/llvm/utils/TableGen/CodeGenRegisters.cpp, line 1253 (as a function)

Referenced in 164 files:

• contrib/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h, 2 times
• contrib/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, 2 times
• contrib/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp, 2 times
• contrib/llvm/lib/CodeGen/AllocationOrder.cpp, line 37
• contrib/llvm/lib/CodeGen/BreakFalseDeps.cpp, line 127
• contrib/llvm/lib/CodeGen/CalcSpillWeights.cpp, line 72
• contrib/llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp, 2 times
• contrib/llvm/lib/CodeGen/DetectDeadLanes.cpp, 5 times
• contrib/llvm/lib/CodeGen/EarlyIfConversion.cpp, line 499
• contrib/llvm/lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp, line 62
• contrib/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp, 2 times
• contrib/llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp, 3 times
• contrib/llvm/lib/CodeGen/GlobalISel/Utils.cpp, line 57
• contrib/llvm/lib/CodeGen/InlineSpiller.cpp, 6 times
• contrib/llvm/lib/CodeGen/LiveDebugVariables.cpp, line 1101
• contrib/llvm/lib/CodeGen/LiveIntervals.cpp, line 1646
• contrib/llvm/lib/CodeGen/LiveRangeEdit.cpp, 3 times
• contrib/llvm/lib/CodeGen/LiveRangeShrink.cpp, 2 times
• contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp, 4 times
• contrib/llvm/lib/CodeGen/MIRParser/MIRParser.cpp, 2 times
• contrib/llvm/lib/CodeGen/MachineFunction.cpp, line 567
• contrib/llvm/lib/CodeGen/MachineInstr.cpp, 3 times
• contrib/llvm/lib/CodeGen/MachineLICM.cpp, 4 times
• contrib/llvm/lib/CodeGen/MachinePipeliner.cpp, 6 times
• contrib/llvm/lib/CodeGen/MachineRegisterInfo.cpp, 3 times
• contrib/llvm/lib/CodeGen/MachineSSAUpdater.cpp, line 62
• contrib/llvm/lib/CodeGen/MachineSink.cpp, 3 times
• contrib/llvm/lib/CodeGen/MachineVerifier.cpp, 4 times
• contrib/llvm/lib/CodeGen/OptimizePHIs.cpp, line 182
• contrib/llvm/lib/CodeGen/PHIElimination.cpp, line 274
• contrib/llvm/lib/CodeGen/PeepholeOptimizer.cpp, 11 times
• contrib/llvm/lib/CodeGen/RegAllocBase.cpp, 2 times
• contrib/llvm/lib/CodeGen/RegAllocFast.cpp, 4 times
• contrib/llvm/lib/CodeGen/RegAllocGreedy.cpp, 10 times
• contrib/llvm/lib/CodeGen/RegAllocPBQP.cpp, 3 times
• contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp, 10 times
• contrib/llvm/lib/CodeGen/RegisterScavenging.cpp, line 659
• contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp, line 134
• contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp, line 366
• contrib/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp, 2 times
• contrib/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp, 12 times
• contrib/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, 3 times
• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp, line 948
• contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp, line 611
• contrib/llvm/lib/CodeGen/SplitKit.cpp, 2 times
• contrib/llvm/lib/CodeGen/TailDuplicator.cpp, 5 times
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp, 4 times
• contrib/llvm/lib/CodeGen/TargetLoweringBase.cpp, line 1058
• contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp, 4 times
• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, 5 times
• contrib/llvm/lib/CodeGen/UnreachableBlockElim.cpp, line 210
• contrib/llvm/lib/CodeGen/VirtRegMap.cpp, 3 times
• contrib/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp, line 89
• contrib/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp, line 520
• contrib/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp, 3 times
• contrib/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp, 4 times
• contrib/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp, line 176
• contrib/llvm/lib/Target/AArch64/AArch64FastISel.cpp, line 3843
• contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp, 11 times
• contrib/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp, 2 times
• contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp, 2 times
• contrib/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp, 4 times
• contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 414
• contrib/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp, 2 times
• contrib/llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp, 12 times
• contrib/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp, 3 times
• contrib/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp, 9 times
• contrib/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, 3 times
• contrib/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp, line 353
• contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp, line 88
• contrib/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp, 12 times
• contrib/llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp, line 216
• contrib/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp, 11 times
• contrib/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp, 3 times
• contrib/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, 6 times
• contrib/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp, line 151
• contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, 3 times
• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, 46 times
• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.h, 3 times
• contrib/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp, 4 times
• contrib/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 1171
• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp, line 1503
• contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h, 2 times
• contrib/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp, 2 times
• contrib/llvm/lib/Target/ARM/A15SDOptimizer.cpp, 8 times
• contrib/llvm/lib/Target/ARM/ARMAsmPrinter.cpp, line 384
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, 2 times
• contrib/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 628
• contrib/llvm/lib/Target/ARM/ARMFastISel.cpp, line 2167
• contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2290
• contrib/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp, 7 times
• contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, 4 times
• contrib/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp, 2 times
• contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp, line 291
• contrib/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp, 2 times
• contrib/llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp, 2 times
• contrib/llvm/lib/Target/BPF/BPFMIPeephole.cpp, line 110
• contrib/llvm/lib/Target/Hexagon/BitTracker.cpp, 2 times
• contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp, 18 times
• contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp, 2 times
• contrib/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp, line 280
• contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp, line 1926
• contrib/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp, 8 times
• contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, 3 times
• contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, 2 times
• contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, 3 times
• contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp, 6 times
• contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp, 5 times
• contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp, 3 times
• contrib/llvm/lib/Target/Hexagon/HexagonPeephole.cpp, line 242
• contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, 10 times
• contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 446
• contrib/llvm/lib/Target/Hexagon/HexagonVExtract.cpp, line 125
• contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp, 2 times
• contrib/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 509
• contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, 21 times
• contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp, line 584
• contrib/llvm/lib/Target/Mips/MipsFastISel.cpp, line 1715
• contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp, 10 times
• contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp, line 141
• contrib/llvm/lib/Target/Mips/MipsOptionRecord.h, 9 times
• contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp, line 129
• contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp, 2 times
• contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp, 2 times
• contrib/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp, 4 times
• contrib/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp, 2 times
• contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp, 8 times
• contrib/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp, line 348
• contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp, line 10113
• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp, 10 times
• contrib/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, 2 times
• contrib/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp, line 59
• contrib/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp, 4 times
• contrib/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp, 2 times
• contrib/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp, line 124
• contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp, line 7159
• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp, 6 times
• contrib/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp, 3 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp, line 51
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp, 4 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp, 5 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp, line 61
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp, 4 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp, 2 times
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, 4 times
• contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp, 3 times
• contrib/llvm/lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp, 2 times
• contrib/llvm/lib/Target/X86/X86CmovConversion.cpp, line 758
• contrib/llvm/lib/Target/X86/X86DomainReassignment.cpp, 5 times
• contrib/llvm/lib/Target/X86/X86FastISel.cpp, 4 times
• contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp, 3 times
• contrib/llvm/lib/Target/X86/X86ISelLowering.cpp, 3 times
• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp, 14 times
• contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp, 18 times
• contrib/llvm/lib/Target/X86/X86OptimizeLEAs.cpp, 4 times
• contrib/llvm/lib/Target/X86/X86RegisterBankInfo.cpp, line 39
• contrib/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp, 5 times
• contrib/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp, line 73
• contrib/llvm/utils/TableGen/CodeGenTarget.h, line 117
• contrib/llvm/utils/TableGen/GlobalISelEmitter.cpp, 2 times
• contrib/llvm/utils/TableGen/RegisterBankEmitter.cpp, line 68