Defined in 2 files as a member:

• contrib/binutils/opcodes/arc-dis.h, line 74 (as a member)
• contrib/llvm/utils/TableGen/CodeGenInstruction.h, line 237 (as a member)

Defined in 5 files as a function:

• contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 657 (as a function)
• contrib/llvm/include/llvm/MC/MCInstrAnalysis.h, line 38 (as a function)
• contrib/llvm/include/llvm/MC/MCInstrDesc.h, line 277 (as a function)
• contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp, line 670 (as a function)
• contrib/llvm/tools/lld/ELF/AArch64ErrataFix.cpp, line 236 (as a function)

Referenced in 65 files:

• contrib/binutils/opcodes/arc-dis.c
  • line 550
  • line 756
• contrib/llvm/include/llvm/CodeGen/MachineInstr.h
  • line 672
  • line 680
• contrib/llvm/include/llvm/MC/MCInstrAnalysis.h, line 39
• contrib/llvm/include/llvm/MC/MCInstrDesc.h
  • line 288
  • line 296
• contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp, line 2985
• contrib/llvm/lib/CodeGen/BranchFolding.cpp
  • line 1326
  • line 1356
• contrib/llvm/lib/CodeGen/IfConversion.cpp
  • line 650
  • line 689
  • line 740
  • line 744
  • line 748
  • line 748
  • line 991
  • line 1786
  • line 2050
• contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
  • line 386
  • line 693
  • line 708
• contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
  • line 1306
  • line 1312
• contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 305
• contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 893
  • line 953
  • line 1127
• contrib/llvm/lib/MC/MCInstrDesc.cpp, line 35
• contrib/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp, line 689
• contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp, line 1655
• contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, line 264
• contrib/llvm/lib/Target/ARC/ARCBranchFinalize.cpp, line 163
• contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, line 4092
• contrib/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
  • line 675
  • line 708
• contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 540
• contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 9175
• contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  • line 529
  • line 533
• contrib/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp, line 239
• contrib/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp, line 63
• contrib/llvm/lib/Target/AVR/AVRInstrInfo.cpp, line 288
• contrib/llvm/lib/Target/BPF/BPFInstrInfo.cpp, line 185
• contrib/llvm/lib/Target/Hexagon/BitTracker.cpp
  • line 848
  • line 931
  • line 1033
  • line 1080
  • line 1111
• contrib/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp
  • line 120
  • line 183
  • line 201
• contrib/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  • line 792
  • line 805
  • line 908
  • line 985
  • line 1035
  • line 2318
• contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp, line 688
• contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
  • line 568
  • line 1488
  • line 1975
  • line 1980
  • line 2370
  • line 2374
  • line 2433
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• contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
  • line 1105
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  • line 1485
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
  • line 545
  • line 547
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
  • line 305
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  • line 330
  • line 417
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
  • line 486
  • line 513
  • line 673
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
  • line 508
  • line 510
• contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
  • line 396
  • line 403
  • line 405
• contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 59
• contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp
  • line 241
  • line 641
  • line 1274
• contrib/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 587
• contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  • line 169
  • line 196
• contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 1780
• contrib/llvm/lib/Target/Mips/MipsBranchExpansion.cpp, line 793
• contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp, line 670
• contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
  • line 361
  • line 695
• contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp, line 609
• contrib/llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
  • line 251
  • line 691
• contrib/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp, line 122
• contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
  • line 61
  • line 179
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• contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  • line 201
  • line 1416
• contrib/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp, line 403
• contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp
  • line 509
  • line 514
• contrib/llvm/lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp
  • line 74
  • line 79
  • line 250
  • line 255
• contrib/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp, line 266
• contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
  • line 402
  • line 484
• contrib/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp, line 111
• contrib/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp, line 145
• contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
  • line 296
  • line 300
  • line 386
  • line 389
  • line 671
• contrib/llvm/lib/Target/X86/X86CondBrFolding.cpp, line 513
• contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
  • line 253
  • line 260
• contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
  • line 2428
  • line 2490
  • line 2566
  • line 3769
  • line 3824
• contrib/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
  • line 582
  • line 642
  • line 861
  • line 986
  • line 1835
• contrib/llvm/tools/lld/ELF/AArch64ErrataFix.cpp, line 366
• contrib/llvm/utils/TableGen/CodeGenInstruction.cpp, line 345
• contrib/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 104
• contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 592