Defined in 1 files as a struct:
Defined in 1 files as a prototype:
Defined in 1 files as a function:
Referenced in 50 files:
- contrib/llvm/include/llvm/CodeGen/LiveInterval.h
- contrib/llvm/include/llvm/CodeGen/LiveIntervals.h
- contrib/llvm/include/llvm/CodeGen/LiveRegUnits.h
- contrib/llvm/include/llvm/CodeGen/MachineBasicBlock.h
- contrib/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 944
- contrib/llvm/include/llvm/CodeGen/RegisterPressure.h
- contrib/llvm/include/llvm/CodeGen/RegisterScavenging.h
- contrib/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
- contrib/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
- contrib/llvm/include/llvm/MC/LaneBitmask.h
- contrib/llvm/include/llvm/MC/MCRegisterInfo.h
- contrib/llvm/lib/CodeGen/BranchFolding.cpp, line 431
- contrib/llvm/lib/CodeGen/DetectDeadLanes.cpp
- contrib/llvm/lib/CodeGen/LiveInterval.cpp
- contrib/llvm/lib/CodeGen/LiveIntervals.cpp
- contrib/llvm/lib/CodeGen/LivePhysRegs.cpp, line 161
- contrib/llvm/lib/CodeGen/LiveRangeCalc.cpp
- contrib/llvm/lib/CodeGen/LiveRangeCalc.h
- contrib/llvm/lib/CodeGen/LiveRangeEdit.cpp, line 250
- contrib/llvm/lib/CodeGen/LiveRegMatrix.cpp, line 86
- contrib/llvm/lib/CodeGen/MIRParser/MIParser.cpp
- contrib/llvm/lib/CodeGen/MachineBasicBlock.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineRegisterInfo.cpp, line 493
- contrib/llvm/lib/CodeGen/MachineScheduler.cpp, line 976
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm/lib/CodeGen/RegisterPressure.cpp
- contrib/llvm/lib/CodeGen/RegisterScavenging.cpp, line 53
- contrib/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
- contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm/lib/CodeGen/SplitKit.cpp
- contrib/llvm/lib/CodeGen/SplitKit.h
- contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp
- contrib/llvm/lib/CodeGen/VirtRegMap.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
- contrib/llvm/lib/Target/AMDGPU/GCNRegPressure.h
- contrib/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp, line 1619
- contrib/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp
- contrib/llvm/lib/Target/Hexagon/RDFGraph.h
- contrib/llvm/lib/Target/Hexagon/RDFLiveness.cpp
- contrib/llvm/lib/Target/Hexagon/RDFLiveness.h, line 50
- contrib/llvm/lib/Target/Hexagon/RDFRegisters.cpp
- contrib/llvm/lib/Target/Hexagon/RDFRegisters.h
- contrib/llvm/utils/TableGen/CodeGenRegisters.cpp
- contrib/llvm/utils/TableGen/CodeGenRegisters.h
- contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp