Defined in 1 files as a member:
Defined in 1 files as a enumerator:
Referenced in 88 files:
- contrib/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
- contrib/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
- contrib/llvm/include/llvm/CodeGen/MachineFunction.h
- contrib/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
- contrib/llvm/include/llvm/CodeGen/MachineMemOperand.h, line 281
- contrib/llvm/include/llvm/CodeGen/PseudoSourceValue.h, line 30
- contrib/llvm/include/llvm/CodeGen/SelectionDAG.h
- contrib/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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- contrib/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
- contrib/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
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- contrib/llvm/lib/CodeGen/ImplicitNullChecks.cpp
- contrib/llvm/lib/CodeGen/LiveDebugValues.cpp
- contrib/llvm/lib/CodeGen/MachineFunction.cpp
- contrib/llvm/lib/CodeGen/MachineInstr.cpp
- contrib/llvm/lib/CodeGen/MachineOperand.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm/lib/CodeGen/StackColoring.cpp
- contrib/llvm/lib/CodeGen/StackSlotColoring.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/CodeGen/TargetLoweringBase.cpp
- contrib/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
- contrib/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
- contrib/llvm/lib/Target/AArch64/AArch64FastISel.cpp
- contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h, line 34
- contrib/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
- contrib/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
- contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.h, line 246
- contrib/llvm/lib/Target/ARC/ARCInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMCallLowering.cpp
- contrib/llvm/lib/Target/ARM/ARMFastISel.cpp
- contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp
- contrib/llvm/lib/Target/ARM/ARMInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
- contrib/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
- contrib/llvm/lib/Target/AVR/AVRInstrInfo.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp
- contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
- contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp
- contrib/llvm/lib/Target/Mips/MipsCallLowering.cpp
- contrib/llvm/lib/Target/Mips/MipsCallLowering.h, line 50
- contrib/llvm/lib/Target/Mips/MipsFastISel.cpp
- contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
- contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
- contrib/llvm/lib/Target/PowerPC/PPCFastISel.cpp
- contrib/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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- contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
- contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
- contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
- contrib/llvm/lib/Target/X86/X86CallLowering.cpp
- contrib/llvm/lib/Target/X86/X86FastISel.cpp
- contrib/llvm/lib/Target/X86/X86ISelLowering.cpp
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- contrib/llvm/lib/Target/X86/X86ISelLowering.h
- contrib/llvm/lib/Target/X86/X86InstrBuilder.h
- contrib/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm/lib/Target/X86/X86InstructionSelector.cpp
- contrib/llvm/lib/Target/XCore/XCoreFrameLowering.cpp
- contrib/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
- sys/cddl/dev/dtrace/x86/dis_tables.c
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