Defined in 2 files as a member:
Defined in 3 files as a function:
Referenced in 81 files:
- contrib/llvm/include/llvm/CodeGen/MachineInstr.h, line 831
- contrib/llvm/include/llvm/CodeGen/ScheduleDAG.h, line 391
- contrib/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm/lib/CodeGen/BranchFolding.cpp
- contrib/llvm/lib/CodeGen/ImplicitNullChecks.cpp
- contrib/llvm/lib/CodeGen/InlineSpiller.cpp, line 448
- contrib/llvm/lib/CodeGen/LiveRangeShrink.cpp, line 135
- contrib/llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
- contrib/llvm/lib/CodeGen/MachineCSE.cpp, line 383
- contrib/llvm/lib/CodeGen/MachineInstr.cpp
- contrib/llvm/lib/CodeGen/MachineLICM.cpp
- contrib/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm/lib/CodeGen/MachineScheduler.cpp, line 1622
- contrib/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm/lib/CodeGen/StackColoring.cpp
- contrib/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm/lib/MC/MCParser/AsmParser.cpp, line 5693
- contrib/llvm/lib/MCA/InstrBuilder.cpp
- contrib/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 345
- contrib/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp, line 644
- contrib/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 2415
- contrib/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
- contrib/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp, line 79
- contrib/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp, line 113
- contrib/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, line 9242
- contrib/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
- contrib/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
- contrib/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
- contrib/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp, line 274
- contrib/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp, line 425
- contrib/llvm/lib/Target/ARM/ARMAsmPrinter.cpp, line 1096
- contrib/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp
- contrib/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp, line 24
- contrib/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp, line 415
- contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2084
- contrib/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp, line 45
- contrib/llvm/lib/Target/ARM/MLxExpansionPass.cpp, line 189
- contrib/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, line 592
- contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, line 2250
- contrib/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp, line 158
- contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp, line 203
- contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, line 163
- contrib/llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp, line 274
- contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
- contrib/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 467
- contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
- contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp, line 59
- contrib/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp, line 193
- contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp, line 2101
- contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
- contrib/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
- contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp, line 244
- contrib/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h, line 35
- contrib/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp, line 95
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 183
- contrib/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp, line 75
- contrib/llvm/lib/Target/X86/AsmParser/X86AsmInstrumentation.cpp, line 425
- contrib/llvm/lib/Target/X86/X86CallFrameOptimization.cpp, line 326
- contrib/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
- contrib/llvm/lib/Target/X86/X86InstrBuilder.h, line 207
- contrib/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp, line 72
- contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
- contrib/llvm/utils/TableGen/CodeGenInstruction.cpp, line 378
- contrib/llvm/utils/TableGen/DAGISelMatcherGen.cpp
- contrib/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 2605
- contrib/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 117
- contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 606