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"L3SliceMask": "0x01",
"UMask": "0x01"
},
{
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"L3ThreadMask": "0x08",
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"UMask": "0x01"
},
{
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"BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types",
"L3ThreadMask": "0x10",
"L3SliceMask": "0x01",
"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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},
{
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},
{
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},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"L3SliceMask": "0x04",
"UMask": "0x01"
},
{
"EventName": "l3fillvicreq.t5.s2.vicblk",
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"L3SliceMask": "0x04",
"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"L3SliceMask": "0x04",
"UMask": "0x01"
},
{
"EventName": "l3fillvicreq.t0.s3.vicblk",
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"L3SliceMask": "0x08",
"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
"EventName": "l3fillvicreq.t3.s3.vicblk",
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x02"
},
{
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{
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},
{
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"UMask": "0x02"
},
{
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"UMask": "0x02"
},
{
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"UMask": "0x02"
},
{
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},
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},
{
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},
{
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},
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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},
{
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},
{
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},
{
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},
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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},
{
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"UMask": "0x04"
},
{
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"L3SliceMask": "0x02",
"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t4.s1.rdblkc_s_vic",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t5.s1.rdblkc_s_vic",
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"L3ThreadMask": "0x20",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t6.s1.rdblkc_s_vic",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t7.s1.rdblkc_s_vic",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t0.s2.rdblkc_s_vic",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t1.s2.rdblkc_s_vic",
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"L3ThreadMask": "0x02",
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"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t2.s2.rdblkc_s_vic",
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"L3ThreadMask": "0x04",
"L3SliceMask": "0x04",
"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t3.s2.rdblkc_s_vic",
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"L3ThreadMask": "0x08",
"L3SliceMask": "0x04",
"UMask": "0x04"
},
{
"EventName": "l3fillvicreq.t4.s2.rdblkc_s_vic",
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"L3ThreadMask": "0x10",
"L3SliceMask": "0x04",
"UMask": "0x04"
},
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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},
{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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},
{
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{
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{
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{
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{
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{
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"UMask": "0x80"
},
{
"EventName": "l3combclstrstate",
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"BriefDescription": "L3 Cache Performance Monitor Counters RequestMiss: L3 miss",
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},
{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
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{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
},
{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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"UMask": "0x01"
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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{
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"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t3.s2.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x08",
"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t4.s2.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x10",
"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t5.s2.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x20",
"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t6.s2.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x40",
"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t7.s2.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x80",
"L3SliceMask": "0x04",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t0.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x01",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t1.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x02",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t2.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x04",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t3.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x08",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t4.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x10",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t5.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x20",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t6.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x40",
"L3SliceMask": "0x08",
"UMask": "0x80"
},
{
"EventName": "l3victimstate.t7.s3.od",
"EventCode": "0x09",
"BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State",
"L3ThreadMask": "0x80",
"L3SliceMask": "0x08",
"UMask": "0x80"
}
]