Defined in 3 files as a member:

• contrib/llvm-project/llvm/include/llvm/CodeGen/RDFRegisters.h, line 136 (as a member)
• contrib/llvm-project/llvm/include/llvm/CodeGen/RegisterClassInfo.h, line 47 (as a member)
• contrib/llvm-project/llvm/include/llvm/MC/MCInstrDesc.h, line 80 (as a member)

Referenced in 55 files:

• contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
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• contrib/llvm-project/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 720
• contrib/llvm-project/llvm/include/llvm/CodeGen/RegisterClassInfo.h, line 74
• contrib/llvm-project/llvm/include/llvm/CodeGen/RegisterScavenging.h
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• contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/Utils.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/LiveIntervals.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/MachineRegisterInfo.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/RDFRegisters.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/RegisterClassInfo.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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• contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp, line 518
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
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• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 6387
• contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp, line 632
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  • line 858
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
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• contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp, line 1193
• contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMFrameLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMISelLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
  • line 169
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• contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 10606
• contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp, line 737
• contrib/llvm-project/llvm/lib/Target/ARM/MVEVPTOptimisationsPass.cpp
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• contrib/llvm-project/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
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• contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp, line 466
• contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.h, line 606
• contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
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• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyPeephole.cpp
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• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
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• contrib/llvm-project/llvm/lib/Target/X86/X86FrameLowering.cpp
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• contrib/llvm-project/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
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• contrib/llvm-project/llvm/lib/Target/X86/X86MCInstLower.cpp
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• contrib/llvm-project/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
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• contrib/llvm-project/llvm/utils/TableGen/CodeGenRegisters.cpp
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• contrib/llvm-project/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
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