Defined in 1 files as a function:

• contrib/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h, line 469 (as a function)

Referenced in 33 files:

• contrib/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h, line 806
• contrib/llvm-project/llvm/lib/CodeGen/LiveDebugVariables.cpp
  • line 1068
  • line 1211
• contrib/llvm-project/llvm/lib/CodeGen/MachineOperand.cpp
  • line 84
  • line 93
• contrib/llvm-project/llvm/lib/CodeGen/MachinePipeliner.cpp, line 408
• contrib/llvm-project/llvm/lib/CodeGen/MachineSink.cpp
  • line 840
  • line 1068
• contrib/llvm-project/llvm/lib/CodeGen/PeepholeOptimizer.cpp
  • line 591
  • line 860
  • line 950
  • line 1077
  • line 1243
• contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp
  • line 771
  • line 868
• contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp
  • line 1339
  • line 1400
• contrib/llvm-project/llvm/lib/CodeGen/TailDuplicator.cpp, line 436
• contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
  • line 220
  • line 224
  • line 225
• contrib/llvm-project/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  • line 1338
  • line 1454
  • line 1472
  • line 1618
• contrib/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp, line 565
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  • line 3642
  • line 5564
• contrib/llvm-project/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp, line 2502
• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp, line 1812
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  • line 287
  • line 709
  • line 823
  • line 845
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 1872
  • line 2581
  • line 2652
  • line 4451
  • line 4456
  • line 4631
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 274
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp, line 139
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  • line 91
  • line 95
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
  • line 379
  • line 397
  • line 1937
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, line 925
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, line 2490
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp, line 1922
• contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, line 1096
• contrib/llvm-project/llvm/lib/Target/Hexagon/RDFCopy.cpp, line 181
• contrib/llvm-project/llvm/lib/Target/Mips/MipsISelLowering.cpp, line 1284
• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  • line 776
  • line 780
  • line 781
  • line 2219
• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCVSXCopy.cpp, line 134
• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
  • line 250
  • line 251
  • line 252
  • line 266
  • line 271
• contrib/llvm-project/llvm/lib/Target/X86/X86DomainReassignment.cpp, line 516
• contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp, line 5506
• contrib/llvm-project/llvm/lib/Target/X86/X86InstructionSelector.cpp
  • line 289
  • line 766