Defined in 1 files as a prototype:

• contrib/llvm-project/llvm/include/llvm/CodeGen/MachineRegisterInfo.h, line 601 (as a prototype)

Defined in 1 files as a function:

• contrib/llvm-project/llvm/lib/CodeGen/MachineRegisterInfo.cpp, line 411 (as a function)

Referenced in 37 files:

• contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
  • line 609
  • line 630
  • line 753
  • line 1369
• contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp, line 647
• contrib/llvm-project/llvm/lib/CodeGen/MachineCombiner.cpp, line 149
• contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp, line 1511
• contrib/llvm-project/llvm/lib/CodeGen/MachinePipeliner.cpp
  • line 870
  • line 925
  • line 932
• contrib/llvm-project/llvm/lib/CodeGen/ModuloSchedule.cpp
  • line 1358
  • line 1388
  • line 1699
  • line 1801
  • line 1890
  • line 1901
• contrib/llvm-project/llvm/lib/CodeGen/RegAllocFast.cpp, line 633
• contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
  • line 684
  • line 686
  • line 696
  • line 697
  • line 876
  • line 880
• contrib/llvm-project/llvm/lib/CodeGen/TargetRegisterInfo.cpp, line 71
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp, line 83
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64FastISel.cpp
  • line 2045
  • line 2077
  • line 4541
  • line 4552
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  • line 1485
  • line 3907
  • line 4409
  • line 4560
• contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp, line 520
• contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  • line 2120
  • line 2131
• contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp, line 198
• contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp, line 437
• contrib/llvm-project/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp, line 62
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
  • line 96
  • line 120
  • line 132
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
  • line 477
  • line 485
  • line 488
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp, line 10968
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  • line 2683
  • line 2701
  • line 2860
  • line 4645
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  • line 1719
  • line 1742
  • line 1752
  • line 1753
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
  • line 396
  • line 486
  • line 527
  • line 569
  • line 590
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
  • line 584
  • line 746
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 317
• contrib/llvm-project/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp, line 82
• contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp, line 2945
• contrib/llvm-project/llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp
  • line 105
  • line 174
  • line 205
  • line 273
• contrib/llvm-project/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 287
• contrib/llvm-project/llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
  • line 85
  • line 109
  • line 148
• contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  • line 380
  • line 398
  • line 408
  • line 473
  • line 475
  • line 1887
  • line 4618
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp, line 764
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h, line 115
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 275
• contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp, line 96
• contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp
  • line 4086
  • line 5392
• contrib/llvm-project/llvm/lib/Target/X86/X86WinAllocaExpander.cpp
  • line 86
  • line 270