Defined in 2 files as a member:
Defined in 3 files as a function:
Referenced in 73 files:
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineInstr.h, line 966
- contrib/llvm-project/llvm/include/llvm/CodeGen/ScheduleDAG.h, line 387
- contrib/llvm-project/llvm/lib/CodeGen/EarlyIfConversion.cpp, line 232
- contrib/llvm-project/llvm/lib/CodeGen/ImplicitNullChecks.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineCSE.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineInstr.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineLICM.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachinePipeliner.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineScheduler.cpp, line 1650
- contrib/llvm-project/llvm/lib/CodeGen/MachineSink.cpp, line 781
- contrib/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm-project/llvm/lib/CodeGen/PeepholeOptimizer.cpp, line 1316
- contrib/llvm-project/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp, line 320
- contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
- contrib/llvm-project/llvm/lib/CodeGen/StackColoring.cpp, line 1117
- contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm-project/llvm/lib/CodeGen/TargetLoweringBase.cpp, line 1073
- contrib/llvm-project/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp, line 1196
- contrib/llvm-project/llvm/lib/MCA/InstrBuilder.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp, line 414
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp, line 467
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp, line 472
- contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp, line 3104
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp, line 113
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp, line 67
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
- contrib/llvm-project/llvm/lib/Target/ARC/ARCInstrInfo.cpp, line 427
- contrib/llvm-project/llvm/lib/Target/ARC/ARCOptAddrMode.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp, line 2164
- contrib/llvm-project/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp, line 796
- contrib/llvm-project/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp, line 43
- contrib/llvm-project/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp, line 510
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp, line 2453
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp, line 630
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
- contrib/llvm-project/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp, line 186
- contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
- contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
- contrib/llvm-project/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp, line 286
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
- contrib/llvm-project/llvm/lib/Target/Sparc/DelaySlotFiller.cpp, line 237
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrBuilder.h, line 31
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp, line 1828
- contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp, line 180
- contrib/llvm-project/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp, line 3381
- contrib/llvm-project/llvm/lib/Target/X86/X86CmovConversion.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86InstrBuilder.h, line 204
- contrib/llvm-project/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
- contrib/llvm-project/llvm/tools/llvm-mca/Views/InstructionInfoView.cpp, line 81
- contrib/llvm-project/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
- contrib/llvm-project/llvm/utils/TableGen/CodeGenInstruction.cpp, line 409
- contrib/llvm-project/llvm/utils/TableGen/DAGISelMatcherGen.cpp
- contrib/llvm-project/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 2943
- contrib/llvm-project/llvm/utils/TableGen/InstrDocsEmitter.cpp, line 114
- contrib/llvm-project/llvm/utils/TableGen/InstrInfoEmitter.cpp, line 753