Defined in 5 files as a member:
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetInstrInfo.h, line 450 (as a member)
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetRegisterInfo.h, line 1020 (as a member)
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp, line 80 (as a member)
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp, line 86 (as a member)
- contrib/llvm-project/llvm/utils/TableGen/GlobalISelEmitter.cpp, line 2555 (as a member)
Referenced in 68 files:
- contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/MachineOperand.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetInstrInfo.h
- contrib/llvm-project/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
- contrib/llvm-project/llvm/lib/CodeGen/DetectDeadLanes.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveInterval.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveIntervalCalc.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveIntervals.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveRangeEdit.cpp
- contrib/llvm-project/llvm/lib/CodeGen/LiveVariables.cpp
- line 198
- line 199
- line 204
- line 252
- line 253
- line 255
- line 259
- line 262
- line 263
- line 291
- line 292
- line 299
- line 340
- line 341
- line 352
- line 353
- line 371
- line 372
- line 375
- line 376
- line 383
- line 385
- line 387
- line 389
- line 390
- line 394
- line 453
- line 460
- line 462
- line 462
- line 463
- line 475
- line 476
- line 479
- line 493
- line 494
- line 495
- contrib/llvm-project/llvm/lib/CodeGen/MIRParser/MIParser.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineInstrBundle.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineOperand.cpp
- contrib/llvm-project/llvm/lib/CodeGen/MachineVerifier.cpp
- contrib/llvm-project/llvm/lib/CodeGen/PeepholeOptimizer.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegisterCoalescer.cpp
- contrib/llvm-project/llvm/lib/CodeGen/RegisterScavenging.cpp
- contrib/llvm-project/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
- contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
- contrib/llvm-project/llvm/lib/CodeGen/TailDuplicator.cpp
- contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp
- contrib/llvm-project/llvm/lib/CodeGen/VirtRegMap.cpp
- contrib/llvm-project/llvm/lib/MC/MCRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp, line 192
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 753
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.h
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp, line 847
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h, line 205
- contrib/llvm-project/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
- contrib/llvm-project/llvm/lib/Target/AVR/AVRRegisterInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AVR/AVRRegisterInfo.h, line 56
- contrib/llvm-project/llvm/lib/Target/BPF/BPFMIPeephole.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp, line 248
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h, line 60
- contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp
- contrib/llvm-project/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCFastISel.cpp
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp, line 339
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h, line 84
- contrib/llvm-project/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86RegisterInfo.cpp
- contrib/llvm-project/llvm/utils/TableGen/CodeGenRegisters.cpp
- contrib/llvm-project/llvm/utils/TableGen/GlobalISelEmitter.cpp