Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
// SPDX-License-Identifier: GPL-2.0
//
// Copyright 2014 Freescale Semiconductor, Inc.

#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6sx-pinfunc.h"

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * The decompressor and also some bootloaders rely on a
	 * pre-existing /chosen node to be available to insert the
	 * command line and merge other ATAGS info.
	 */
	chosen {};

	aliases {
		can0 = &flexcan1;
		can1 = &flexcan2;
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
		gpio5 = &gpio6;
		gpio6 = &gpio7;
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		mmc3 = &usdhc4;
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
		spi0 = &ecspi1;
		spi1 = &ecspi2;
		spi2 = &ecspi3;
		spi3 = &ecspi4;
		spi4 = &ecspi5;
		usbphy0 = &usbphy1;
		usbphy1 = &usbphy2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				996000  1250000
				792000  1175000
				396000  1075000
				198000	975000
			>;
			fsl,soc-operating-points = <
				/* ARM kHz  SOC uV */
				996000      1175000
				792000      1175000
				396000      1175000
				198000	    1175000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			#cooling-cells = <2>;
			clocks = <&clks IMX6SX_CLK_ARM>,
				 <&clks IMX6SX_CLK_PLL2_PFD2>,
				 <&clks IMX6SX_CLK_STEP>,
				 <&clks IMX6SX_CLK_PLL1_SW>,
				 <&clks IMX6SX_CLK_PLL1_SYS>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			soc-supply = <&reg_soc>;
			nvmem-cells = <&cpu_speed_grade>;
			nvmem-cell-names = "speed_grade";
		};
	};

	ckil: clock-ckil {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32768>;
		clock-output-names = "ckil";
	};

	osc: clock-osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24000000>;
		clock-output-names = "osc";
	};

	ipp_di0: clock-ipp-di0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di0";
	};

	ipp_di1: clock-ipp-di1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "ipp_di1";
	};

	anaclk1: clock-anaclk1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "anaclk1";
	};

	anaclk2: clock-anaclk2 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
		clock-output-names = "anaclk2";
	};

	tempmon: tempmon {
		compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
		interrupt-parent = <&gpc>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		fsl,tempmon = <&anatop>;
		nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
		nvmem-cell-names = "calib", "temp_grade";
		clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-parent = <&gpc>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
	};

	usbphynop1: usbphynop1 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&gpc>;
		ranges;

		ocram_s: sram@8f8000 {
			compatible = "mmio-sram";
			reg = <0x008f8000 0x4000>;
			clocks = <&clks IMX6SX_CLK_OCRAM_S>;
		};

		ocram: sram@900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x20000>;
			clocks = <&clks IMX6SX_CLK_OCRAM>;
		};

		intc: interrupt-controller@a01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x00a01000 0x1000>,
			      <0x00a00100 0x100>;
			interrupt-parent = <&intc>;
		};

		L2: l2-cache@a02000 {
			compatible = "arm,pl310-cache";
			reg = <0x00a02000 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <4 2 3>;
			arm,data-latency = <4 2 3>;
		};

		gpu: gpu@1800000 {
			compatible = "vivante,gc";
			reg = <0x01800000 0x4000>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SX_CLK_GPU>,
				 <&clks IMX6SX_CLK_GPU>,
				 <&clks IMX6SX_CLK_GPU>;
			clock-names = "bus", "core", "shader";
			power-domains = <&pd_pu>;
		};

		dma_apbh: dma-apbh@1804000 {
			compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
			reg = <0x01804000 0x2000>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
			#dma-cells = <1>;
			dma-channels = <4>;
			clocks = <&clks IMX6SX_CLK_APBH_DMA>;
		};

		gpmi: gpmi-nand@1806000{
			compatible = "fsl,imx6sx-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "bch";
			clocks = <&clks IMX6SX_CLK_GPMI_IO>,
				 <&clks IMX6SX_CLK_GPMI_APB>,
				 <&clks IMX6SX_CLK_GPMI_BCH>,
				 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
				 <&clks IMX6SX_CLK_PER1_BCH>;
			clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
				      "gpmi_bch_apb", "per1_bch";
			dmas = <&dma_apbh 0>;
			dma-names = "rx-tx";
			status = "disabled";
		};

		aips1: bus@2000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02000000 0x100000>;
			ranges;

			spba-bus@2000000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02000000 0x40000>;
				ranges;

				spdif: spdif@2004000 {
					compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
					reg = <0x02004000 0x4000>;
					interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&sdma 14 18 0>,
					       <&sdma 15 18 0>;
					dma-names = "rx", "tx";
					clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
						 <&clks IMX6SX_CLK_OSC>,
						 <&clks IMX6SX_CLK_SPDIF>,
						 <&clks 0>, <&clks 0>, <&clks 0>,
						 <&clks IMX6SX_CLK_IPG>,
						 <&clks 0>, <&clks 0>,
						 <&clks IMX6SX_CLK_SPBA>;
					clock-names = "core", "rxtx0",
						      "rxtx1", "rxtx2",
						      "rxtx3", "rxtx4",
						      "rxtx5", "rxtx6",
						      "rxtx7", "spba";
					status = "disabled";
				};

				ecspi1: spi@2008000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02008000 0x4000>;
					interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI1>,
						 <&clks IMX6SX_CLK_ECSPI1>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi2: spi@200c000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x0200c000 0x4000>;
					interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI2>,
						 <&clks IMX6SX_CLK_ECSPI2>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi3: spi@2010000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02010000 0x4000>;
					interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI3>,
						 <&clks IMX6SX_CLK_ECSPI3>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				ecspi4: spi@2014000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
					reg = <0x02014000 0x4000>;
					interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ECSPI4>,
						 <&clks IMX6SX_CLK_ECSPI4>;
					clock-names = "ipg", "per";
					status = "disabled";
				};

				uart1: serial@2020000 {
					compatible = "fsl,imx6sx-uart",
						     "fsl,imx6q-uart", "fsl,imx21-uart";
					reg = <0x02020000 0x4000>;
					interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_UART_IPG>,
						 <&clks IMX6SX_CLK_UART_SERIAL>;
					clock-names = "ipg", "per";
					dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
					dma-names = "rx", "tx";
					status = "disabled";
				};

				esai: esai@2024000 {
					reg = <0x02024000 0x4000>;
					interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
						 <&clks IMX6SX_CLK_ESAI_MEM>,
						 <&clks IMX6SX_CLK_ESAI_EXTAL>,
						 <&clks IMX6SX_CLK_ESAI_IPG>,
						 <&clks IMX6SX_CLK_SPBA>;
					clock-names = "core", "mem", "extal",
						      "fsys", "spba";
					status = "disabled";
				};

				ssi1: ssi@2028000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x02028000 0x4000>;
					interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
						 <&clks IMX6SX_CLK_SSI1>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi2: ssi@202c000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x0202c000 0x4000>;
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
						 <&clks IMX6SX_CLK_SSI2>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				ssi3: ssi@2030000 {
					#sound-dai-cells = <0>;
					compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
					reg = <0x02030000 0x4000>;
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
						 <&clks IMX6SX_CLK_SSI3>;
					clock-names = "ipg", "baud";
					dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					status = "disabled";
				};

				asrc: asrc@2034000 {
					reg = <0x02034000 0x4000>;
					interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
						 <&clks IMX6SX_CLK_ASRC_IPG>,
						 <&clks IMX6SX_CLK_SPDIF>,
						 <&clks IMX6SX_CLK_SPBA>;
					clock-names = "mem", "ipg", "asrck", "spba";
					dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
					       <&sdma 19 20 1>, <&sdma 20 20 1>,
					       <&sdma 21 20 1>, <&sdma 22 20 1>;
					dma-names = "rxa", "rxb", "rxc",
						    "txa", "txb", "txc";
					status = "okay";
				};
			};

			pwm1: pwm@2080000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02080000 0x4000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM1>,
					 <&clks IMX6SX_CLK_PWM1>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm2: pwm@2084000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02084000 0x4000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM2>,
					 <&clks IMX6SX_CLK_PWM2>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm3: pwm@2088000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x02088000 0x4000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM3>,
					 <&clks IMX6SX_CLK_PWM3>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm4: pwm@208c000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x0208c000 0x4000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM4>,
					 <&clks IMX6SX_CLK_PWM4>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			flexcan1: can@2090000 {
				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02090000 0x4000>;
				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
					 <&clks IMX6SX_CLK_CAN1_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
				status = "disabled";
			};

			flexcan2: can@2094000 {
				compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
				reg = <0x02094000 0x4000>;
				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
					 <&clks IMX6SX_CLK_CAN2_SERIAL>;
				clock-names = "ipg", "per";
				fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
				status = "disabled";
			};

			gpt: timer@2098000 {
				compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
				reg = <0x02098000 0x4000>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_GPT_BUS>,
					 <&clks IMX6SX_CLK_GPT_3M>;
				clock-names = "ipg", "per";
			};

			gpio1: gpio@209c000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x0209c000 0x4000>;
				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 5 26>;
			};

			gpio2: gpio@20a0000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a0000 0x4000>;
				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 31 20>;
			};

			gpio3: gpio@20a4000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a4000 0x4000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 51 29>;
			};

			gpio4: gpio@20a8000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020a8000 0x4000>;
				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 80 32>;
			};

			gpio5: gpio@20ac000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020ac000 0x4000>;
				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 112 24>;
			};

			gpio6: gpio@20b0000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020b0000 0x4000>;
				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
			};

			gpio7: gpio@20b4000 {
				compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
				reg = <0x020b4000 0x4000>;
				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
			};

			kpp: keypad@20b8000 {
				compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
				reg = <0x020b8000 0x4000>;
				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			wdog1: watchdog@20bc000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x020bc000 0x4000>;
				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
			};

			wdog2: watchdog@20c0000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x020c0000 0x4000>;
				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			clks: clock-controller@20c4000 {
				compatible = "fsl,imx6sx-ccm";
				reg = <0x020c4000 0x4000>;
				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
				#clock-cells = <1>;
				clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>;
				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
			};

			anatop: anatop@20c8000 {
				compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
					     "syscon", "simple-mfd";
				reg = <0x020c8000 0x1000>;
				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;

				reg_vdd1p1: regulator-1p1 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd1p1";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
					anatop-reg-offset = <0x110>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <4>;
					anatop-min-voltage = <800000>;
					anatop-max-voltage = <1375000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd3p0: regulator-3p0 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd3p0";
					regulator-min-microvolt = <2800000>;
					regulator-max-microvolt = <3150000>;
					regulator-always-on;
					anatop-reg-offset = <0x120>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2625000>;
					anatop-max-voltage = <3400000>;
					anatop-enable-bit = <0>;
				};

				reg_vdd2p5: regulator-2p5 {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vdd2p5";
					regulator-min-microvolt = <2250000>;
					regulator-max-microvolt = <2750000>;
					regulator-always-on;
					anatop-reg-offset = <0x130>;
					anatop-vol-bit-shift = <8>;
					anatop-vol-bit-width = <5>;
					anatop-min-bit-val = <0>;
					anatop-min-voltage = <2100000>;
					anatop-max-voltage = <2875000>;
					anatop-enable-bit = <0>;
				};

				reg_arm: regulator-vddcore {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddarm";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <0>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <24>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_pcie: regulator-vddpcie {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddpcie";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <9>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <26>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};

				reg_soc: regulator-vddsoc {
					compatible = "fsl,anatop-regulator";
					regulator-name = "vddsoc";
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1450000>;
					regulator-always-on;
					anatop-reg-offset = <0x140>;
					anatop-vol-bit-shift = <18>;
					anatop-vol-bit-width = <5>;
					anatop-delay-reg-offset = <0x170>;
					anatop-delay-bit-shift = <28>;
					anatop-delay-bit-width = <2>;
					anatop-min-bit-val = <1>;
					anatop-min-voltage = <725000>;
					anatop-max-voltage = <1450000>;
				};
			};

			usbphy1: usbphy@20c9000 {
				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
				reg = <0x020c9000 0x1000>;
				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBPHY1>;
				fsl,anatop = <&anatop>;
			};

			usbphy2: usbphy@20ca000 {
				compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
				reg = <0x020ca000 0x1000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBPHY2>;
				fsl,anatop = <&anatop>;
			};

			snvs: snvs@20cc000 {
				compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
				reg = <0x020cc000 0x4000>;

				snvs_rtc: snvs-rtc-lp {
					compatible = "fsl,sec-v4.0-mon-rtc-lp";
					regmap = <&snvs>;
					offset = <0x34>;
					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
				};

				snvs_poweroff: snvs-poweroff {
					compatible = "syscon-poweroff";
					regmap = <&snvs>;
					offset = <0x38>;
					value = <0x60>;
					mask = <0x60>;
					status = "disabled";
				};

				snvs_pwrkey: snvs-powerkey {
					compatible = "fsl,sec-v4.0-pwrkey";
					regmap = <&snvs>;
					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
					linux,keycode = <KEY_POWER>;
					wakeup-source;
					status = "disabled";
				};
			};

			epit1: epit@20d0000 {
				reg = <0x020d0000 0x4000>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			epit2: epit@20d4000 {
				reg = <0x020d4000 0x4000>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			};

			src: reset-controller@20d8000 {
				compatible = "fsl,imx6sx-src", "fsl,imx51-src";
				reg = <0x020d8000 0x4000>;
				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
				#reset-cells = <1>;
			};

			gpc: gpc@20dc000 {
				compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
				reg = <0x020dc000 0x4000>;
				interrupt-controller;
				#interrupt-cells = <3>;
				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "ipg";

				pgc {
					#address-cells = <1>;
					#size-cells = <0>;

					power-domain@0 {
						reg = <0>;
						#power-domain-cells = <0>;
					};

					pd_pu: power-domain@1 {
						reg = <1>;
						#power-domain-cells = <0>;
						power-supply = <&reg_soc>;
						clocks = <&clks IMX6SX_CLK_GPU>;
					};

					pd_disp: power-domain@2 {
						reg = <2>;
						#power-domain-cells = <0>;
						clocks = <&clks IMX6SX_CLK_PXP_AXI>,
							 <&clks IMX6SX_CLK_DISPLAY_AXI>,
							 <&clks IMX6SX_CLK_LCDIF1_PIX>,
							 <&clks IMX6SX_CLK_LCDIF_APB>,
							 <&clks IMX6SX_CLK_LCDIF2_PIX>,
							 <&clks IMX6SX_CLK_CSI>,
							 <&clks IMX6SX_CLK_VADC>;
					};

					pd_pci: power-domain@3 {
						reg = <3>;
						#power-domain-cells = <0>;
						power-supply = <&reg_pcie>;
					};
				};
			};

			iomuxc: pinctrl@20e0000 {
				compatible = "fsl,imx6sx-iomuxc";
				reg = <0x020e0000 0x4000>;
			};

			gpr: iomuxc-gpr@20e4000 {
				compatible = "fsl,imx6sx-iomuxc-gpr",
					     "fsl,imx6q-iomuxc-gpr", "syscon";
				reg = <0x020e4000 0x4000>;
			};

			sdma: sdma@20ec000 {
				compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
				reg = <0x020ec000 0x4000>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>,
					 <&clks IMX6SX_CLK_SDMA>;
				clock-names = "ipg", "ahb";
				#dma-cells = <3>;
				/* imx6sx reuses imx6q sdma firmware */
				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
			};
		};

		aips2: bus@2100000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02100000 0x100000>;
			ranges;

			crypto: crypto@2100000 {
				compatible = "fsl,sec-v4.0";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x2100000 0x10000>;
				ranges = <0 0x2100000 0x10000>;
				interrupt-parent = <&intc>;
				clocks = <&clks IMX6SX_CLK_CAAM_MEM>,
					 <&clks IMX6SX_CLK_CAAM_ACLK>,
					 <&clks IMX6SX_CLK_CAAM_IPG>,
					 <&clks IMX6SX_CLK_EIM_SLOW>;
				clock-names = "mem", "aclk", "ipg", "emi_slow";

				sec_jr0: jr@1000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x1000 0x1000>;
					interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
				};

				sec_jr1: jr@2000 {
					compatible = "fsl,sec-v4.0-job-ring";
					reg = <0x2000 0x1000>;
					interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			usbotg1: usb@2184000 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184000 0x200>;
				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphy1>;
				fsl,usbmisc = <&usbmisc 0>;
				fsl,anatop = <&anatop>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbotg2: usb@2184200 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184200 0x200>;
				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphy2>;
				fsl,usbmisc = <&usbmisc 1>;
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbh: usb@2184400 {
				compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
				reg = <0x02184400 0x200>;
				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
				fsl,usbphy = <&usbphynop1>;
				fsl,usbmisc = <&usbmisc 2>;
				phy_type = "hsic";
				fsl,anatop = <&anatop>;
				dr_mode = "host";
				ahb-burst-config = <0x0>;
				tx-burst-size-dword = <0x10>;
				rx-burst-size-dword = <0x10>;
				status = "disabled";
			};

			usbmisc: usbmisc@2184800 {
				#index-cells = <1>;
				compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
				reg = <0x02184800 0x200>;
				clocks = <&clks IMX6SX_CLK_USBOH3>;
			};

			fec1: ethernet@2188000 {
				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
				reg = <0x02188000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ENET>,
					 <&clks IMX6SX_CLK_ENET_AHB>,
					 <&clks IMX6SX_CLK_ENET_PTP>,
					 <&clks IMX6SX_CLK_ENET_REF>,
					 <&clks IMX6SX_CLK_ENET_PTP>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,num-tx-queues = <3>;
				fsl,num-rx-queues = <3>;
				fsl,stop-mode = <&gpr 0x10 3>;
				status = "disabled";
			};

			mlb: mlb@218c000 {
				reg = <0x0218c000 0x4000>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_MLB>;
				status = "disabled";
			};

			usdhc1: usdhc@2190000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02190000 0x4000>;
				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC1>,
					 <&clks IMX6SX_CLK_USDHC1>,
					 <&clks IMX6SX_CLK_USDHC1>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc2: usdhc@2194000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02194000 0x4000>;
				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC2>,
					 <&clks IMX6SX_CLK_USDHC2>,
					 <&clks IMX6SX_CLK_USDHC2>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc3: usdhc@2198000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x02198000 0x4000>;
				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC3>,
					 <&clks IMX6SX_CLK_USDHC3>,
					 <&clks IMX6SX_CLK_USDHC3>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			usdhc4: usdhc@219c000 {
				compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
				reg = <0x0219c000 0x4000>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_USDHC4>,
					 <&clks IMX6SX_CLK_USDHC4>,
					 <&clks IMX6SX_CLK_USDHC4>;
				clock-names = "ipg", "ahb", "per";
				bus-width = <4>;
				status = "disabled";
			};

			i2c1: i2c@21a0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a0000 0x4000>;
				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C1>;
				status = "disabled";
			};

			i2c2: i2c@21a4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a4000 0x4000>;
				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C2>;
				status = "disabled";
			};

			i2c3: i2c@21a8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021a8000 0x4000>;
				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C3>;
				status = "disabled";
			};

			memory-controller@21b0000 {
				compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
				reg = <0x021b0000 0x4000>;
				clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;
			};

			fec2: ethernet@21b4000 {
				compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
				reg = <0x021b4000 0x4000>;
				interrupt-names = "int0", "pps";
				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ENET>,
					 <&clks IMX6SX_CLK_ENET_AHB>,
					 <&clks IMX6SX_CLK_ENET_PTP>,
					 <&clks IMX6SX_CLK_ENET2_REF_125M>,
					 <&clks IMX6SX_CLK_ENET_PTP>;
				clock-names = "ipg", "ahb", "ptp",
					      "enet_clk_ref", "enet_out";
				fsl,stop-mode = <&gpr 0x10 4>;
				status = "disabled";
			};

			weim: weim@21b8000 {
				#address-cells = <2>;
				#size-cells = <1>;
				compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
				reg = <0x021b8000 0x4000>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
				fsl,weim-cs-gpr = <&gpr>;
				status = "disabled";
			};

			ocotp: ocotp-ctrl@21bc000 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "fsl,imx6sx-ocotp", "syscon";
				reg = <0x021bc000 0x4000>;
				clocks = <&clks IMX6SX_CLK_OCOTP>;

				cpu_speed_grade: speed-grade@10 {
					reg = <0x10 4>;
				};

				tempmon_calib: calib@38 {
					reg = <0x38 4>;
				};

				tempmon_temp_grade: temp-grade@20 {
					reg = <0x20 4>;
				};
			};

			sai1: sai@21d4000 {
				compatible = "fsl,imx6sx-sai";
				reg = <0x021d4000 0x4000>;
				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
					 <&clks IMX6SX_CLK_SAI1>,
					 <&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "rx", "tx";
				dmas = <&sdma 31 24 0>, <&sdma 32 24 0>;
				status = "disabled";
			};

			audmux: audmux@21d8000 {
				compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
				reg = <0x021d8000 0x4000>;
				status = "disabled";
			};

			sai2: sai@21dc000 {
				compatible = "fsl,imx6sx-sai";
				reg = <0x021dc000 0x4000>;
				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
					 <&clks IMX6SX_CLK_SAI2>,
					 <&clks 0>, <&clks 0>;
				clock-names = "bus", "mclk1", "mclk2", "mclk3";
				dma-names = "rx", "tx";
				dmas = <&sdma 33 24 0>, <&sdma 34 24 0>;
				status = "disabled";
			};

			qspi1: spi@21e0000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-qspi";
				reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_QSPI1>,
					 <&clks IMX6SX_CLK_QSPI1>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			qspi2: spi@21e4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-qspi";
				reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
				reg-names = "QuadSPI", "QuadSPI-memory";
				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_QSPI2>,
					 <&clks IMX6SX_CLK_QSPI2>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			uart2: serial@21e8000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021e8000 0x4000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart3: serial@21ec000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021ec000 0x4000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart4: serial@21f0000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f0000 0x4000>;
				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			uart5: serial@21f4000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x021f4000 0x4000>;
				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			i2c4: i2c@21f8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
				reg = <0x021f8000 0x4000>;
				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_I2C4>;
				status = "disabled";
			};
		};

		aips3: bus@2200000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x02200000 0x100000>;
			ranges;

			spba-bus@2240000 {
				compatible = "fsl,spba-bus", "simple-bus";
				#address-cells = <1>;
				#size-cells = <1>;
				reg = <0x02240000 0x40000>;
				ranges;

				csi1: csi@2214000 {
					reg = <0x02214000 0x4000>;
					interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
						 <&clks IMX6SX_CLK_CSI>,
						 <&clks IMX6SX_CLK_DCIC1>;
					clock-names = "disp-axi", "csi_mclk", "dcic";
					status = "disabled";
				};

				pxp: pxp@2218000 {
					compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp";
					reg = <0x02218000 0x4000>;
					interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_PXP_AXI>;
					clock-names = "axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				csi2: csi@221c000 {
					reg = <0x0221c000 0x4000>;
					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
					clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
						 <&clks IMX6SX_CLK_CSI>,
						 <&clks IMX6SX_CLK_DCIC2>;
					clock-names = "disp-axi", "csi_mclk", "dcic";
					status = "disabled";
				};

				lcdif1: lcdif@2220000 {
					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
					reg = <0x02220000 0x4000>;
					interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>;
					clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
						 <&clks IMX6SX_CLK_LCDIF_APB>,
						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
					clock-names = "pix", "axi", "disp_axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				lcdif2: lcdif@2224000 {
					compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
					reg = <0x02224000 0x4000>;
					interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>;
					clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
						 <&clks IMX6SX_CLK_LCDIF_APB>,
						 <&clks IMX6SX_CLK_DISPLAY_AXI>;
					clock-names = "pix", "axi", "disp_axi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};

				vadc: vadc@2228000 {
					reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
					reg-names = "vadc-vafe", "vadc-vdec";
					clocks = <&clks IMX6SX_CLK_VADC>,
						 <&clks IMX6SX_CLK_CSI>;
					clock-names = "vadc", "csi";
					power-domains = <&pd_disp>;
					status = "disabled";
				};
			};

			adc1: adc@2280000 {
				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
				reg = <0x02280000 0x4000>;
				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "adc";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							 <20000000>;
				status = "disabled";
			};

			adc2: adc@2284000 {
				compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
				reg = <0x02284000 0x4000>;
				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				clock-names = "adc";
				fsl,adck-max-frequency = <30000000>, <40000000>,
							 <20000000>;
				status = "disabled";
			};

			wdog3: watchdog@2288000 {
				compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
				reg = <0x02288000 0x4000>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_IPG>;
				status = "disabled";
			};

			ecspi5: spi@228c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
				reg = <0x0228c000 0x4000>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_ECSPI5>,
					 <&clks IMX6SX_CLK_ECSPI5>;
				clock-names = "ipg", "per";
				status = "disabled";
			};

			uart6: serial@22a0000 {
				compatible = "fsl,imx6sx-uart",
					     "fsl,imx6q-uart", "fsl,imx21-uart";
				reg = <0x022a0000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_UART_IPG>,
					 <&clks IMX6SX_CLK_UART_SERIAL>;
				clock-names = "ipg", "per";
				dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
				dma-names = "rx", "tx";
				status = "disabled";
			};

			pwm5: pwm@22a4000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022a4000 0x4000>;
				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM5>,
					 <&clks IMX6SX_CLK_PWM5>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm6: pwm@22a8000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022a8000 0x4000>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM6>,
					 <&clks IMX6SX_CLK_PWM6>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm7: pwm@22ac000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x022ac000 0x4000>;
				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM7>,
					 <&clks IMX6SX_CLK_PWM7>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};

			pwm8: pwm@22b0000 {
				compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
				reg = <0x0022b0000 0x4000>;
				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks IMX6SX_CLK_PWM8>,
					 <&clks IMX6SX_CLK_PWM8>;
				clock-names = "ipg", "per";
				#pwm-cells = <2>;
			};
		};

		pcie: pcie@8ffc000 {
			compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
			reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>;
			reg-names = "dbi", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			bus-range = <0x00 0xff>;
			ranges = <0x81000000 0 0          0x08f80000 0 0x00010000 /* downstream I/O */
				  0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
			num-lanes = <1>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "msi";
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0x7>;
			interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
					<0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
				 <&clks IMX6SX_CLK_LVDS1_OUT>,
				 <&clks IMX6SX_CLK_PCIE_REF_125M>,
				 <&clks IMX6SX_CLK_DISPLAY_AXI>;
			clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
			power-domains = <&pd_disp>, <&pd_pci>;
			power-domain-names = "pcie", "pcie_phy";
			status = "disabled";
		};
	};
};