Defined in 1 files as a function:
Referenced in 39 files:
- contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
- contrib/llvm-project/llvm/lib/CodeGen/ImplicitNullChecks.cpp, line 532
- contrib/llvm-project/llvm/lib/CodeGen/MachineCopyPropagation.cpp, line 521
- contrib/llvm-project/llvm/lib/CodeGen/TargetInstrInfo.cpp, line 1013
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp, line 427
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp, line 435
- contrib/llvm-project/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp, line 420
- contrib/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp, line 742
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp, line 1525
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp, line 947
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp, line 536
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp, line 343
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp, line 922
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
- contrib/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp, line 1924
- contrib/llvm-project/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp, line 75
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp, line 976
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp, line 1004
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp, line 1659
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
- contrib/llvm-project/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
- contrib/llvm-project/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp, line 323
- contrib/llvm-project/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp, line 738
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp, line 561
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp, line 800
- contrib/llvm-project/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp, line 168
- contrib/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp, line 765
- contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp
- contrib/llvm-project/llvm/lib/Target/X86/X86WinAllocaExpander.cpp, line 182