// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
 *
 * Copyright 2014-2015 Freescale Semiconductor, Inc.
 * Copyright 2018 NXP
 *
 * Mingkai Hu <Mingkai.hu@freescale.com>
 */

/dts-v1/;
#include "fsl-ls1043a.dtsi"

/ {
	model = "LS1043A RDB Board";
	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&i2c0 {
	status = "okay";
	ina220@40 {
		compatible = "ti,ina220";
		reg = <0x40>;
		shunt-resistor = <1000>;
	};
	adt7461a@4c {
		compatible = "adi,adt7461";
		reg = <0x4c>;
	};
	eeprom@52 {
		compatible = "atmel,24c512";
		reg = <0x52>;
	};
	eeprom@53 {
		compatible = "atmel,24c512";
		reg = <0x53>;
	};
	rtc@68 {
		compatible = "pericom,pt7c4338";
		reg = <0x68>;
	};
};

&ifc {
	status = "okay";
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;

		nor@0,0 {
			compatible = "cfi-flash";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x0 0x0 0x8000000>;
			big-endian;
			bank-width = <2>;
			device-width = <1>;
		};

		nand@1,0 {
			compatible = "fsl,ifc-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x1 0x0 0x10000>;
		};

		cpld: board-control@2,0 {
			compatible = "fsl,ls1043ardb-cpld";
			reg = <0x2 0x0 0x0000100>;
		};
};

&dspi0 {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
		reg = <0>;
		spi-max-frequency = <1000000>; /* input clock */
	};

	slic@2 {
		compatible = "maxim,ds26522";
		reg = <2>;
		spi-max-frequency = <2000000>;
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};

	slic@3 {
		compatible = "maxim,ds26522";
		reg = <3>;
		spi-max-frequency = <2000000>;
		fsl,spi-cs-sck-delay = <100>;
		fsl,spi-sck-cs-delay = <50>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

#include "fsl-ls1043-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy1>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e2000 {
		phy-handle = <&qsgmii_phy2>;
		phy-connection-type = "qsgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii-id";
	};

	ethernet@e8000 {
		phy-handle = <&qsgmii_phy3>;
		phy-connection-type = "qsgmii";
	};

	ethernet@ea000 {
		phy-handle = <&qsgmii_phy4>;
		phy-connection-type = "qsgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		phy-handle = <&aqr105_phy>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {
		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		rgmii_phy2: ethernet-phy@2 {
			reg = <0x2>;
		};

		qsgmii_phy1: ethernet-phy@4 {
			reg = <0x4>;
		};

		qsgmii_phy2: ethernet-phy@5 {
			reg = <0x5>;
		};

		qsgmii_phy3: ethernet-phy@6 {
			reg = <0x6>;
		};

		qsgmii_phy4: ethernet-phy@7 {
			reg = <0x7>;
		};
	};

	mdio@fd000 {
		aqr105_phy: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c45";
			interrupts = <0 132 4>;
			reg = <0x1>;
		};
	};
};

&uqe {
	ucc_hdlc: ucc@2000 {
		compatible = "fsl,ucc-hdlc";
		rx-clock-name = "clk8";
		tx-clock-name = "clk9";
		fsl,rx-sync-clock = "rsync_pin";
		fsl,tx-sync-clock = "tsync_pin";
		fsl,tx-timeslot-mask = <0xfffffffe>;
		fsl,rx-timeslot-mask = <0xfffffffe>;
		fsl,tdm-framer-type = "e1";
		fsl,tdm-id = <0>;
		fsl,siram-entry-id = <0>;
		fsl,tdm-interface;
	};
};