# SPDX-License-Identifier: GPL-2.0
#
# For a description of the syntax of this configuration file,
# see Documentation/kbuild/kconfig-language.rst.
#
config [31mCONFIG_OPENRISC[0m
def_bool y
select [31mCONFIG_ARCH_32BIT_OFF_T[0m
select [31mCONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE[0m
select [31mCONFIG_OF[0m
select [31mCONFIG_OF_EARLY_FLATTREE[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_HANDLE_DOMAIN_IRQ[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_SPARSE_IRQ[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_GENERIC_IRQ_PROBE[0m
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_GENERIC_IOMAP[0m
select [31mCONFIG_GENERIC_CPU_DEVICES[0m
select [31mCONFIG_HAVE_UID16[0m
select [31mCONFIG_GENERIC_ATOMIC64[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m
select [31mCONFIG_GENERIC_STRNCPY_FROM_USER[0m
select [31mCONFIG_GENERIC_STRNLEN_USER[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
select [31mCONFIG_MODULES_USE_ELF_RELA[0m
select [31mCONFIG_HAVE_DEBUG_STACKOVERFLOW[0m
select [31mCONFIG_OR1K_PIC[0m
select [31mCONFIG_CPU_NO_EFFICIENT_FFS[0m if ![31mCONFIG_OPENRISC_HAVE_INST_FF1[0m
select [31mCONFIG_ARCH_USE_QUEUED_SPINLOCKS[0m
select [31mCONFIG_ARCH_USE_QUEUED_RWLOCKS[0m
select [31mCONFIG_OMPIC[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_ARCH_WANT_FRAME_POINTERS[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select MMU_GATHER_NO_RANGE if [31mCONFIG_MMU[0m
config [31mCONFIG_CPU_BIG_ENDIAN[0m
def_bool y
config [31mCONFIG_MMU[0m
def_bool y
config [31mCONFIG_GENERIC_HWEIGHT[0m
def_bool y
config [31mCONFIG_NO_IOPORT_MAP[0m
def_bool y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
def_bool y
# For now, use generic checksum functions
#These can be reimplemented in assembly later if so inclined
config [31mCONFIG_GENERIC_CSUM[0m
def_bool y
config [31mCONFIG_STACKTRACE_SUPPORT[0m
def_bool y
config [31mCONFIG_LOCKDEP_SUPPORT[0m
def_bool y
menu "Processor type and features"
choice
prompt "Subarchitecture"
default [31mCONFIG_OR1K_1200[0m
config [31mCONFIG_OR1K_1200[0m
bool "OR1200"
help
Generic OpenRISC 1200 architecture
endchoice
config [31mCONFIG_DCACHE_WRITETHROUGH[0m
bool "Have write through data caches"
default n
help
Select this if your implementation features write through data caches.
Selecting 'N' here will allow the kernel to force flushing of data
caches at relevant times. Most OpenRISC implementations support write-
through data caches.
If unsure say N here
config [31mCONFIG_OPENRISC_BUILTIN_DTB[0m
string "Builtin DTB"
default ""
menu "Class II Instructions"
config [31mCONFIG_OPENRISC_HAVE_INST_FF1[0m
bool "Have instruction l.ff1"
default y
help
Select this if your implementation has the Class II instruction l.ff1
config [31mCONFIG_OPENRISC_HAVE_INST_FL1[0m
bool "Have instruction l.fl1"
default y
help
Select this if your implementation has the Class II instruction l.fl1
config [31mCONFIG_OPENRISC_HAVE_INST_MUL[0m
bool "Have instruction l.mul for hardware multiply"
default y
help
Select this if your implementation has a hardware multiply instruction
config [31mCONFIG_OPENRISC_HAVE_INST_DIV[0m
bool "Have instruction l.div for hardware divide"
default y
help
Select this if your implementation has a hardware divide instruction
endmenu
config [31mCONFIG_NR_CPUS[0m
int "Maximum number of CPUs (2-32)"
range 2 32
depends on [31mCONFIG_SMP[0m
default "2"
config [31mCONFIG_SMP[0m
bool "Symmetric Multi-Processing support"
help
This enables support for systems with more than one CPU. If you have
a system with only one CPU, say N. If you have a system with more
than one CPU, say Y.
If you don't know what to do here, say N.
source "kernel/Kconfig.hz"
config [31mCONFIG_OPENRISC_NO_SPR_SR_DSX[0m
bool "use SPR_SR_DSX software emulation" if [31mCONFIG_OR1K_1200[0m
default y
help
SPR_SR_DSX bit is status register bit indicating whether
the last exception has happened in delay slot.
OpenRISC architecture makes it optional to have it implemented
in hardware and the OR1200 does not have it.
Say N here if you know that your OpenRISC processor has
SPR_SR_DSX bit implemented. Say Y if you are unsure.
config [31mCONFIG_OPENRISC_HAVE_SHADOW_GPRS[0m
bool "Support for shadow gpr files" if ![31mCONFIG_SMP[0m
default y if [31mCONFIG_SMP[0m
help
Say Y here if your OpenRISC processor features shadowed
register files. They will in such case be used as a
scratch reg storage on exception entry.
On [31mCONFIG_SMP[0m systems, this feature is mandatory.
On a unicore system it's safe to say N here if you are unsure.
config [31mCONFIG_CMDLINE[0m
string "Default kernel command string"
default ""
help
On some architectures there is currently no way for the boot loader
to pass arguments to the kernel. For these architectures, you should
supply some command-line options at build time by entering them
here.
menu "Debugging options"
config [31mCONFIG_JUMP_UPON_UNHANDLED_EXCEPTION[0m
bool "Try to die gracefully"
default y
help
Now this puts kernel into infinite loop after first oops. Till
your kernel crashes this doesn't have any influence.
Say Y if you are unsure.
config [31mCONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK[0m
bool "Check for possible ESR exception bug"
default n
help
This option enables some checks that might expose some problems
in kernel.
Say N if you are unsure.
endmenu
endmenu