# SPDX-License-Identifier: GPL-2.0-only
menu "IRQ chip support"
config [31mCONFIG_IRQCHIP[0m
def_bool y
depends on [31mCONFIG_OF_IRQ[0m
config [31mCONFIG_ARM_GIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_ARM_GIC_PM[0m
bool
depends on [31mCONFIG_PM[0m
select [31mCONFIG_ARM_GIC[0m
config [31mCONFIG_ARM_GIC_MAX_NR[0m
int
depends on [31mCONFIG_ARM_GIC[0m
default 2 if [31mCONFIG_ARCH_REALVIEW[0m
default 1
config [31mCONFIG_ARM_GIC_V2M[0m
bool
depends on [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_PCI_MSI[0m
config [31mCONFIG_GIC_NON_BANKED[0m
bool
config [31mCONFIG_ARM_GIC_V3[0m
bool
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_PARTITION_PERCPU[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_ARM_GIC_V3_ITS[0m
bool
select [31mCONFIG_GENERIC_MSI_IRQ_DOMAIN[0m
default [31mCONFIG_ARM_GIC_V3[0m
config [31mCONFIG_ARM_GIC_V3_ITS_PCI[0m
bool
depends on [31mCONFIG_ARM_GIC_V3_ITS[0m
depends on [31mCONFIG_PCI[0m
depends on [31mCONFIG_PCI_MSI[0m
default [31mCONFIG_ARM_GIC_V3_ITS[0m
config [31mCONFIG_ARM_GIC_V3_ITS_FSL_MC[0m
bool
depends on [31mCONFIG_ARM_GIC_V3_ITS[0m
depends on [31mCONFIG_FSL_MC_BUS[0m
default [31mCONFIG_ARM_GIC_V3_ITS[0m
config [31mCONFIG_ARM_NVIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_ARM_VIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
config [31mCONFIG_ARM_VIC_NR[0m
int
default 4 if [31mCONFIG_ARCH_S5PV210[0m
default 2
depends on [31mCONFIG_ARM_VIC[0m
help
The maximum number of VICs available in the system, for
power management.
config [31mCONFIG_ARMADA_370_XP_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_PCI_MSI[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_ALPINE_MSI[0m
bool
depends on [31mCONFIG_PCI[0m
select [31mCONFIG_PCI_MSI[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_AL_FIC[0m
bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
depends on [31mCONFIG_OF[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support Amazon's Annapurna Labs Fabric Interrupt Controller.
config [31mCONFIG_ATMEL_AIC_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_ATMEL_AIC5_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_I8259[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BCM6345_L1_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_BCM7038_L1_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_BCM7120_L2_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BRCMSTB_L2_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_DAVINCI_AINTC[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_DAVINCI_CP_INTC[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_DW_APB_ICTL[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_FARADAY_FTINTC010[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_HISILICON_IRQ_MBIGEN[0m
bool
select [31mCONFIG_ARM_GIC_V3[0m
select [31mCONFIG_ARM_GIC_V3_ITS[0m
config [31mCONFIG_IMGPDC_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_IXP4XX_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_MADERA_IRQ[0m
tristate
config [31mCONFIG_IRQ_MIPS_CPU[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_GENERIC_IRQ_IPI[0m if [31mCONFIG_SYS_SUPPORTS_MULTITHREADING[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m if [31mCONFIG_GENERIC_IRQ_IPI[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_CLPS711X_IRQCHIP[0m
bool
depends on [31mCONFIG_ARCH_CLPS711X[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
default y
config [31mCONFIG_OMPIC[0m
bool
config [31mCONFIG_OR1K_PIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_OMAP_IRQCHIP[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_ORION_IRQCHIP[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_MULTI_HANDLER[0m
config [31mCONFIG_PIC32_EVIC[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_JCORE_AIC[0m
bool "J-Core integrated AIC" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support for the J-Core integrated AIC.
config [31mCONFIG_RDA_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_RENESAS_INTC_IRQPIN[0m
bool "Renesas INTC External IRQ Pin Support" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Enable support for the Renesas Interrupt Controller for external
interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
config [31mCONFIG_RENESAS_IRQC[0m
bool "Renesas R-Mobile APE6 and R-Car IRQC support" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Enable support for the Renesas Interrupt Controller for external
devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
config [31mCONFIG_RENESAS_RZA1_IRQC[0m
bool "Renesas RZ/A1 IRQC support" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
Enable support for the Renesas RZ/[31mCONFIG_A1[0m Interrupt Controller, to use up
to 8 external interrupts with configurable sense select.
config [31mCONFIG_ST_IRQCHIP[0m
bool
select [31mCONFIG_REGMAP[0m
select [31mCONFIG_MFD_SYSCON[0m
help
Enables SysCfg Controlled IRQs on STi based platforms.
config [31mCONFIG_TANGO_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_TB10X_IRQC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_TS4800_IRQ[0m
tristate "TS-4800 IRQ controller"
select [31mCONFIG_IRQ_DOMAIN[0m
depends on [31mCONFIG_HAS_IOMEM[0m
depends on [31mCONFIG_SOC_IMX51[0m || [31mCONFIG_COMPILE_TEST[0m
help
Support for the TS-4800 [31mCONFIG_FPGA[0m IRQ controller
config [31mCONFIG_VERSATILE_FPGA_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_VERSATILE_FPGA_IRQ_NR[0m
int
default 4
depends on [31mCONFIG_VERSATILE_FPGA_IRQ[0m
config [31mCONFIG_XTENSA_MX[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK[0m
config [31mCONFIG_XILINX_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_IRQ_CROSSBAR[0m
bool
help
Support for a CROSSBAR ip that precedes the main interrupt controller.
The primary irqchip invokes the crossbar's callback which inturn allocates
a free irq and configures the IP. Thus the peripheral interrupts are
routed to one of the free irqchip interrupt lines.
config [31mCONFIG_KEYSTONE_IRQ[0m
tristate "Keystone 2 IRQ controller IP"
depends on [31mCONFIG_ARCH_KEYSTONE[0m
help
Support for Texas Instruments Keystone 2 IRQ controller IP which
is part of the Keystone 2 IPC mechanism
config [31mCONFIG_MIPS_GIC[0m
bool
select [31mCONFIG_GENERIC_IRQ_IPI[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_MIPS_CM[0m
config [31mCONFIG_INGENIC_IRQ[0m
bool
depends on [31mCONFIG_MACH_INGENIC[0m
default y
config [31mCONFIG_INGENIC_TCU_IRQ[0m
bool "Ingenic JZ47xx TCU interrupt controller"
default [31mCONFIG_MACH_INGENIC[0m
depends on [31mCONFIG_MIPS[0m || [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_MFD_SYSCON[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
help
Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
JZ47xx SoCs.
If unsure, say N.
config [31mCONFIG_RENESAS_H8300H_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_RENESAS_H8S_INTC[0m
bool "Renesas H8S Interrupt Controller Support" if [31mCONFIG_COMPILE_TEST[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Enable support for the Renesas H8/300 Interrupt Controller, as found
on Renesas H8S SoCs.
config [31mCONFIG_IMX_GPCV2[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
help
Enables the wakeup IRQs for IMX platforms with GPCv2 block
config [31mCONFIG_IRQ_MXS[0m
def_bool y if [31mCONFIG_MACH_ASM9260[0m || [31mCONFIG_ARCH_MXS[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_STMP_DEVICE[0m
config [31mCONFIG_MSCC_OCELOT_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_MVEBU_GICP[0m
bool
config [31mCONFIG_MVEBU_ICU[0m
bool
config [31mCONFIG_MVEBU_ODMI[0m
bool
select [31mCONFIG_GENERIC_MSI_IRQ_DOMAIN[0m
config [31mCONFIG_MVEBU_PIC[0m
bool
config [31mCONFIG_MVEBU_SEI[0m
bool
config [31mCONFIG_LS_SCFG_MSI[0m
def_bool y if [31mCONFIG_SOC_LS1021A[0m || [31mCONFIG_ARCH_LAYERSCAPE[0m
depends on [31mCONFIG_PCI[0m && [31mCONFIG_PCI_MSI[0m
config [31mCONFIG_PARTITION_PERCPU[0m
bool
config [31mCONFIG_EZNPS_GIC[0m
bool "NPS400 Global Interrupt Manager (GIM)"
depends on [31mCONFIG_ARC[0m || ([31mCONFIG_COMPILE_TEST[0m && ![31mCONFIG_64BIT[0m)
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support the EZchip NPS400 global interrupt controller
config [31mCONFIG_STM32_EXTI[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_QCOM_IRQ_COMBINER[0m
bool "QCOM IRQ combiner support"
depends on [31mCONFIG_ARCH_QCOM[0m && [31mCONFIG_ACPI[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
Say yes here to add support for the IRQ combiner devices embedded
in Qualcomm Technologies chips.
config [31mCONFIG_IRQ_UNIPHIER_AIDET[0m
bool "UniPhier AIDET support" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_ARCH_UNIPHIER[0m || [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_UNIPHIER[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
Support for the UniPhier AIDET ([31mCONFIG_ARM[0m Interrupt Detector).
config [31mCONFIG_MESON_IRQ_GPIO[0m
bool "Meson GPIO Interrupt Multiplexer"
depends on [31mCONFIG_ARCH_MESON[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
Support Meson SoC Family GPIO Interrupt Multiplexer
config [31mCONFIG_GOLDFISH_PIC[0m
bool "Goldfish programmable interrupt controller"
depends on [31mCONFIG_MIPS[0m && ([31mCONFIG_GOLDFISH[0m || [31mCONFIG_COMPILE_TEST[0m)
select [31mCONFIG_IRQ_DOMAIN[0m
help
Say yes here to enable Goldfish interrupt controller driver used
for Goldfish based virtual platforms.
config [31mCONFIG_QCOM_PDC[0m
bool "QCOM PDC"
depends on [31mCONFIG_ARCH_QCOM[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
Power Domain Controller driver to manage and configure wakeup
IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
config [31mCONFIG_CSKY_MPINTC[0m
bool "C-SKY Multi Processor Interrupt Controller"
depends on [31mCONFIG_CSKY[0m
help
Say yes here to enable [31mCONFIG_C[0m-SKY [31mCONFIG_SMP[0m interrupt controller driver used
for [31mCONFIG_C[0m-SKY [31mCONFIG_SMP[0m system.
In fact it's not mmio map in hw and it use ld/st to visit the
controller's register inside CPU.
config [31mCONFIG_CSKY_APB_INTC[0m
bool "C-SKY APB Interrupt Controller"
depends on [31mCONFIG_CSKY[0m
help
Say yes here to enable [31mCONFIG_C[0m-SKY APB interrupt controller driver used
by [31mCONFIG_C[0m-SKY single core SOC system. It use mmio map apb-bus to visit
the controller's register.
config [31mCONFIG_IMX_IRQSTEER[0m
bool "i.MX IRQSTEER support"
depends on [31mCONFIG_ARCH_MXC[0m || [31mCONFIG_COMPILE_TEST[0m
default [31mCONFIG_ARCH_MXC[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
config [31mCONFIG_LS1X_IRQ[0m
bool "Loongson-1 Interrupt Controller"
depends on [31mCONFIG_MACH_LOONGSON32[0m
default y
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
help
Support for the Loongson-1 platform Interrupt Controller.
config [31mCONFIG_TI_SCI_INTR_IRQCHIP[0m
bool
depends on [31mCONFIG_TI_SCI_PROTOCOL[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
help
This enables the irqchip driver support for K3 Interrupt router
over TI System Control Interface available on some new TI's SoCs.
If you wish to use interrupt router irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
config [31mCONFIG_TI_SCI_INTA_IRQCHIP[0m
bool
depends on [31mCONFIG_TI_SCI_PROTOCOL[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_TI_SCI_INTA_MSI_DOMAIN[0m
help
This enables the irqchip driver support for K3 Interrupt aggregator
over TI System Control Interface available on some new TI's SoCs.
If you wish to use interrupt aggregator irq resources managed by the
TI System Controller, say Y here. Otherwise, say N.
endmenu
config [31mCONFIG_SIFIVE_PLIC[0m
bool "SiFive Platform-Level Interrupt Controller"
depends on [31mCONFIG_RISCV[0m
help
This enables support for the PLIC chip found in SiFive (and
potentially other) RISC-V systems. The PLIC controls devices
interrupts and connects them to each core's local interrupt
controller. Aside from timer and software interrupts, all other
interrupt sources are subordinate to the PLIC.
If you don't know what to do here, say Y.