menu "TI OMAP/AM/DM/DRA Family"
depends on [31mCONFIG_ARCH_MULTI_V6[0m || [31mCONFIG_ARCH_MULTI_V7[0m
config [31mCONFIG_ARCH_OMAP2[0m
bool "TI OMAP2"
depends on [31mCONFIG_ARCH_MULTI_V6[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_CPU_V6[0m
select [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
config [31mCONFIG_ARCH_OMAP3[0m
bool "TI OMAP3"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
select [31mCONFIG_PM_OPP[0m if [31mCONFIG_PM[0m
select [31mCONFIG_PM[0m if [31mCONFIG_CPU_IDLE[0m
select [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
select [31mCONFIG_ARM_ERRATA_430973[0m
config [31mCONFIG_ARCH_OMAP4[0m
bool "TI OMAP4"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ARM_ERRATA_720789[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_HAVE_ARM_SCU[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_HAVE_ARM_TWD[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
select [31mCONFIG_OMAP_INTERCONNECT_BARRIER[0m
select [31mCONFIG_PL310_ERRATA_588369[0m if [31mCONFIG_CACHE_L2X0[0m
select [31mCONFIG_PL310_ERRATA_727915[0m if [31mCONFIG_CACHE_L2X0[0m
select [31mCONFIG_PM_OPP[0m if [31mCONFIG_PM[0m
select [31mCONFIG_PM[0m if [31mCONFIG_CPU_IDLE[0m
select [31mCONFIG_ARM_ERRATA_754322[0m
select [31mCONFIG_ARM_ERRATA_775420[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
config [31mCONFIG_SOC_OMAP5[0m
bool "TI OMAP5"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_HAVE_ARM_SCU[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_HAVE_ARM_ARCH_TIMER[0m
select [31mCONFIG_ARM_ERRATA_798181[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
select [31mCONFIG_OMAP_INTERCONNECT_BARRIER[0m
select [31mCONFIG_PM_OPP[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ZONE_DMA[0m if [31mCONFIG_ARM_LPAE[0m
config [31mCONFIG_SOC_AM33XX[0m
bool "TI AM33XX"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
config [31mCONFIG_SOC_AM43XX[0m
bool "TI AM43x"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_MACH_OMAP_GENERIC[0m
select [31mCONFIG_MIGHT_HAVE_CACHE_L2X0[0m
select [31mCONFIG_HAVE_ARM_SCU[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m
select [31mCONFIG_HAVE_ARM_TWD[0m
select [31mCONFIG_ARM_ERRATA_754322[0m
select [31mCONFIG_ARM_ERRATA_775420[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
config [31mCONFIG_SOC_DRA7XX[0m
bool "TI DRA7XX"
depends on [31mCONFIG_ARCH_MULTI_V7[0m
select [31mCONFIG_ARCH_OMAP2PLUS[0m
select [31mCONFIG_ARM_CPU_SUSPEND[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_HAVE_ARM_SCU[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_HAVE_ARM_ARCH_TIMER[0m
select [31mCONFIG_IRQ_CROSSBAR[0m
select [31mCONFIG_ARM_ERRATA_798181[0m if [31mCONFIG_SMP[0m
select [31mCONFIG_OMAP_INTERCONNECT[0m
select [31mCONFIG_OMAP_INTERCONNECT_BARRIER[0m
select [31mCONFIG_PM_OPP[0m if [31mCONFIG_PM[0m
select [31mCONFIG_ZONE_DMA[0m if [31mCONFIG_ARM_LPAE[0m
config [31mCONFIG_ARCH_OMAP2PLUS[0m
bool
select [31mCONFIG_ARCH_HAS_BANDGAP[0m
select [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m
select [31mCONFIG_ARCH_OMAP[0m
select [31mCONFIG_CLKSRC_MMIO[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_MACH_OMAP_GENERIC[0m
select [31mCONFIG_MEMORY[0m
select [31mCONFIG_MFD_SYSCON[0m
select [31mCONFIG_OMAP_DM_TIMER[0m
select [31mCONFIG_OMAP_GPMC[0m
select [31mCONFIG_PINCTRL[0m
select [31mCONFIG_SOC_BUS[0m
select [31mCONFIG_OMAP_IRQCHIP[0m
select [31mCONFIG_CLKSRC_TI_32K[0m
help
Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
config [31mCONFIG_OMAP_INTERCONNECT_BARRIER[0m
bool
select [31mCONFIG_ARM_HEAVY_MB[0m
if [31mCONFIG_ARCH_OMAP2PLUS[0m
menu "TI OMAP2/3/4 Specific Features"
config [31mCONFIG_ARCH_OMAP2PLUS_TYPICAL[0m
bool "Typical OMAP configuration"
default y
select [31mCONFIG_AEABI[0m
select [31mCONFIG_HIGHMEM[0m
select [31mCONFIG_I2C[0m
select [31mCONFIG_I2C_OMAP[0m
select [31mCONFIG_MENELAUS[0m if [31mCONFIG_ARCH_OMAP2[0m
select [31mCONFIG_NEON[0m if [31mCONFIG_CPU_V7[0m
select [31mCONFIG_PM[0m
select [31mCONFIG_REGULATOR[0m
select [31mCONFIG_REGULATOR_FIXED_VOLTAGE[0m
select [31mCONFIG_TWL4030_CORE[0m if [31mCONFIG_ARCH_OMAP3[0m || [31mCONFIG_ARCH_OMAP4[0m
select [31mCONFIG_TWL4030_POWER[0m if [31mCONFIG_ARCH_OMAP3[0m || [31mCONFIG_ARCH_OMAP4[0m
select [31mCONFIG_VFP[0m
help
Compile a kernel suitable for booting most boards
config [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
bool "OMAP2 SDRAM Controller support"
config [31mCONFIG_SOC_HAS_REALTIME_COUNTER[0m
bool "Real time free running counter"
depends on [31mCONFIG_SOC_OMAP5[0m || [31mCONFIG_SOC_DRA7XX[0m
default y
comment "OMAP Core Type"
depends on [31mCONFIG_ARCH_OMAP2[0m
config [31mCONFIG_SOC_OMAP2420[0m
bool "OMAP2420 support"
depends on [31mCONFIG_ARCH_OMAP2[0m
default y
select [31mCONFIG_OMAP_DM_TIMER[0m
select [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
config [31mCONFIG_SOC_OMAP2430[0m
bool "OMAP2430 support"
depends on [31mCONFIG_ARCH_OMAP2[0m
default y
select [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
config [31mCONFIG_SOC_OMAP3430[0m
bool "OMAP3430 support"
depends on [31mCONFIG_ARCH_OMAP3[0m
default y
select [31mCONFIG_SOC_HAS_OMAP2_SDRC[0m
config [31mCONFIG_SOC_TI81XX[0m
bool "TI81XX support"
depends on [31mCONFIG_ARCH_OMAP3[0m
default y
config [31mCONFIG_OMAP_PACKAGE_CBC[0m
bool
config [31mCONFIG_OMAP_PACKAGE_CBB[0m
bool
config [31mCONFIG_OMAP_PACKAGE_CUS[0m
bool
config [31mCONFIG_OMAP_PACKAGE_CBP[0m
bool
comment "OMAP Legacy Platform Data Board Type"
depends on [31mCONFIG_ARCH_OMAP2PLUS[0m
config [31mCONFIG_MACH_OMAP_GENERIC[0m
bool
config [31mCONFIG_MACH_OMAP2_TUSB6010[0m
bool
depends on [31mCONFIG_ARCH_OMAP2[0m && [31mCONFIG_SOC_OMAP2420[0m
default y if [31mCONFIG_MACH_NOKIA_N8X0[0m
config [31mCONFIG_MACH_OMAP3517EVM[0m
bool "OMAP3517/ AM3517 EVM board"
depends on [31mCONFIG_ARCH_OMAP3[0m
default y
config [31mCONFIG_MACH_OMAP3_PANDORA[0m
bool "OMAP3 Pandora"
depends on [31mCONFIG_ARCH_OMAP3[0m
default y
select [31mCONFIG_OMAP_PACKAGE_CBB[0m
config [31mCONFIG_MACH_NOKIA_N810[0m
bool
config [31mCONFIG_MACH_NOKIA_N810_WIMAX[0m
bool
config [31mCONFIG_MACH_NOKIA_N8X0[0m
bool "Nokia N800/N810"
depends on [31mCONFIG_SOC_OMAP2420[0m
default y
select [31mCONFIG_MACH_NOKIA_N810[0m
select [31mCONFIG_MACH_NOKIA_N810_WIMAX[0m
config [31mCONFIG_OMAP3_SDRC_AC_TIMING[0m
bool "Enable SDRC AC timing register changes"
depends on [31mCONFIG_ARCH_OMAP3[0m
default n
help
If you know that none of your system initiators will attempt to
access SDRAM during [31mCONFIG_CORE[0m DVFS, select Y here. This should boost
SDRAM performance at lower [31mCONFIG_CORE[0m OPPs. There are relatively few
users who will wish to say yes at this point - almost everyone will
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
endmenu
endif
config [31mCONFIG_OMAP5_ERRATA_801819[0m
bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
depends on [31mCONFIG_SOC_OMAP5[0m || [31mCONFIG_SOC_DRA7XX[0m
help
[31mCONFIG_A[0m livelock can occur in the L2 cache arbitration that might prevent
a snoop from completing. Under certain conditions this can cause the
system to deadlock.
endmenu