1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 | /* * Copyright 2008 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef __MACH_BF518_H__ #define __MACH_BF518_H__ #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ #define IMASK_IVG15 0x8000 #define IMASK_IVG14 0x4000 #define IMASK_IVG13 0x2000 #define IMASK_IVG12 0x1000 #define IMASK_IVG11 0x0800 #define IMASK_IVG10 0x0400 #define IMASK_IVG9 0x0200 #define IMASK_IVG8 0x0100 #define IMASK_IVG7 0x0080 #define IMASK_IVGTMR 0x0040 #define IMASK_IVGHW 0x0020 /***************************/ #define BFIN_DSUBBANKS 4 #define BFIN_DWAYS 2 #define BFIN_DLINES 64 #define BFIN_ISUBBANKS 4 #define BFIN_IWAYS 4 #define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 #define WAY01_L 0x3 #define WAY2_L 0x4 #define WAY02_L 0x5 #define WAY12_L 0x6 #define WAY012_L 0x7 #define WAY3_L 0x8 #define WAY03_L 0x9 #define WAY13_L 0xA #define WAY013_L 0xB #define WAY32_L 0xC #define WAY320_L 0xD #define WAY321_L 0xE #define WAYALL_L 0xF #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ /********************************* EBIU Settings ************************************/ #define AMBCTL0VAL (([31mCONFIG_BANK_1[0m << 16) | [31mCONFIG_BANK_0[0m) #define AMBCTL1VAL (([31mCONFIG_BANK_3[0m << 16) | [31mCONFIG_BANK_2[0m) #ifdef [31mCONFIG_C_AMBEN_ALL[0m #define V_AMBEN AMBEN_ALL #endif #ifdef [31mCONFIG_C_AMBEN[0m #define V_AMBEN 0x0 #endif #ifdef [31mCONFIG_C_AMBEN_B0[0m #define V_AMBEN AMBEN_B0 #endif #ifdef [31mCONFIG_C_AMBEN_B0_B1[0m #define V_AMBEN AMBEN_B0_B1 #endif #ifdef [31mCONFIG_C_AMBEN_B0_B1_B2[0m #define V_AMBEN AMBEN_B0_B1_B2 #endif #ifdef [31mCONFIG_C_AMCKEN[0m #define V_AMCKEN AMCKEN #else #define V_AMCKEN 0x0 #endif #ifdef [31mCONFIG_C_CDPRIO[0m #define V_CDPRIO 0x100 #else #define V_CDPRIO 0x0 #endif #define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) /**************************** Hysteresis Settings ****************************/ #ifdef [31mCONFIG_BFIN_HYSTERESIS_CONTROL[0m #ifdef [31mCONFIG_GPIO_HYST_PORTF_0_7[0m #define HYST_PORTF_0_7 (1 << 0) #else #define HYST_PORTF_0_7 (0 << 0) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTF_8_9[0m #define HYST_PORTF_8_9 (1 << 2) #else #define HYST_PORTF_8_9 (0 << 2) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTF_10[0m #define HYST_PORTF_10 (1 << 4) #else #define HYST_PORTF_10 (0 << 4) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTF_11[0m #define HYST_PORTF_11 (1 << 6) #else #define HYST_PORTF_11 (0 << 6) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTF_12_13[0m #define HYST_PORTF_12_13 (1 << 8) #else #define HYST_PORTF_12_13 (0 << 8) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTF_14_15[0m #define HYST_PORTF_14_15 (1 << 10) #else #define HYST_PORTF_14_15 (0 << 10) #endif #define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \ HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15) #ifdef [31mCONFIG_GPIO_HYST_PORTG_0[0m #define HYST_PORTG_0 (1 << 0) #else #define HYST_PORTG_0 (0 << 0) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_1_4[0m #define HYST_PORTG_1_4 (1 << 2) #else #define HYST_PORTG_1_4 (0 << 2) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_5_6[0m #define HYST_PORTG_5_6 (1 << 4) #else #define HYST_PORTG_5_6 (0 << 4) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_7_8[0m #define HYST_PORTG_7_8 (1 << 6) #else #define HYST_PORTG_7_8 (0 << 6) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_9[0m #define HYST_PORTG_9 (1 << 8) #else #define HYST_PORTG_9 (0 << 8) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_10[0m #define HYST_PORTG_10 (1 << 10) #else #define HYST_PORTG_10 (0 << 10) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_11_13[0m #define HYST_PORTG_11_13 (1 << 12) #else #define HYST_PORTG_11_13 (0 << 12) #endif #ifdef [31mCONFIG_GPIO_HYST_PORTG_14_15[0m #define HYST_PORTG_14_15 (1 << 14) #else #define HYST_PORTG_14_15 (0 << 14) #endif #define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \ HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \ HYST_PORTG_11_13 | HYST_PORTG_14_15) #ifdef [31mCONFIG_GPIO_HYST_PORTH_0_7[0m #define HYST_PORTH_0_7 (1 << 0) #else #define HYST_PORTH_0_7 (0 << 0) #endif #define HYST_PORTH_0_15 (HYST_PORTH_0_7) #ifdef [31mCONFIG_NONEGPIO_HYST_NMI_RST_BMODE[0m #define HYST_NMI_RST_BMODE (1 << 2) #else #define HYST_NMI_RST_BMODE (0 << 2) #endif #ifdef [31mCONFIG_NONEGPIO_HYST_JTAG[0m #define HYST_JTAG (1 << 4) #else #define HYST_JTAG (0 << 4) #endif #define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG) #define HYST_NONEGPIO_MASK (0x3C) #endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */ #ifdef [31mCONFIG_BF518[0m #define CPU "BF518" #define CPUID 0x27e8 #endif #ifdef [31mCONFIG_BF516[0m #define CPU "BF516" #define CPUID 0x27e8 #endif #ifdef [31mCONFIG_BF514[0m #define CPU "BF514" #define CPUID 0x27e8 #endif #ifdef [31mCONFIG_BF512[0m #define CPU "BF512" #define CPUID 0x27e8 #endif #ifndef CPU #error "Unknown CPU type - This kernel doesn't seem to be configured properly" #endif #endif /* __MACH_BF518_H__ */ |