# # [31mCONFIG_FPGA[0m framework configuration # menu "FPGA Configuration Support" config [31mCONFIG_FPGA[0m tristate "FPGA Configuration Framework" help Say Y here if you want support for configuring FPGAs from the kernel. The [31mCONFIG_FPGA[0m framework adds a [31mCONFIG_FPGA[0m manager class and [31mCONFIG_FPGA[0m manager drivers. if [31mCONFIG_FPGA[0m config [31mCONFIG_FPGA_REGION[0m tristate "FPGA Region" depends on [31mCONFIG_OF[0m && [31mCONFIG_FPGA_BRIDGE[0m help [31mCONFIG_FPGA[0m Regions allow loading [31mCONFIG_FPGA[0m images under control of the Device Tree. config [31mCONFIG_FPGA_MGR_SOCFPGA[0m tristate "Altera SOCFPGA FPGA Manager" depends on [31mCONFIG_ARCH_SOCFPGA[0m || [31mCONFIG_COMPILE_TEST[0m help [31mCONFIG_FPGA[0m manager driver support for Altera SOCFPGA. config [31mCONFIG_FPGA_MGR_SOCFPGA_A10[0m tristate "Altera SoCFPGA Arria10" depends on [31mCONFIG_ARCH_SOCFPGA[0m || [31mCONFIG_COMPILE_TEST[0m select [31mCONFIG_REGMAP_MMIO[0m help [31mCONFIG_FPGA[0m manager driver support for Altera Arria10 SoCFPGA. config [31mCONFIG_FPGA_MGR_ZYNQ_FPGA[0m tristate "Xilinx Zynq FPGA" depends on [31mCONFIG_ARCH_ZYNQ[0m || [31mCONFIG_COMPILE_TEST[0m depends on [31mCONFIG_HAS_DMA[0m help [31mCONFIG_FPGA[0m manager driver support for Xilinx Zynq FPGAs. config [31mCONFIG_FPGA_BRIDGE[0m tristate "FPGA Bridge Framework" depends on [31mCONFIG_OF[0m help Say Y here if you want to support bridges connected between host processors and FPGAs or between FPGAs. config [31mCONFIG_SOCFPGA_FPGA_BRIDGE[0m tristate "Altera SoCFPGA FPGA Bridges" depends on [31mCONFIG_ARCH_SOCFPGA[0m && [31mCONFIG_FPGA_BRIDGE[0m help Say Y to enable drivers for [31mCONFIG_FPGA[0m bridges for Altera SOCFPGA devices. config [31mCONFIG_ALTERA_FREEZE_BRIDGE[0m tristate "Altera FPGA Freeze Bridge" depends on [31mCONFIG_ARCH_SOCFPGA[0m && [31mCONFIG_FPGA_BRIDGE[0m help Say Y to enable drivers for Altera [31mCONFIG_FPGA[0m Freeze bridges. [31mCONFIG_A[0m freeze bridge is a bridge that exists in the [31mCONFIG_FPGA[0m fabric to isolate one region of the [31mCONFIG_FPGA[0m from the busses while that region is being reprogrammed. endif # [31mCONFIG_FPGA[0m endmenu |