config [31mCONFIG_ARM64[0m
def_bool y
select [31mCONFIG_ACPI_CCA_REQUIRED[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ACPI_GENERIC_GSI[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ACPI_REDUCED_HARDWARE_ONLY[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ACPI_MCFG[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ACPI_SPCR_TABLE[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ARCH_CLOCKSOURCE_DATA[0m
select [31mCONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED[0m
select [31mCONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_ARCH_HAS_ELF_RANDOMIZE[0m
select [31mCONFIG_ARCH_HAS_GCOV_PROFILE_ALL[0m
select [31mCONFIG_ARCH_HAS_GIGANTIC_PAGE[0m
select [31mCONFIG_ARCH_HAS_KCOV[0m
select [31mCONFIG_ARCH_HAS_SG_CHAIN[0m
select [31mCONFIG_ARCH_HAS_TICK_BROADCAST[0m if [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m
select [31mCONFIG_ARCH_USE_CMPXCHG_LOCKREF[0m
select [31mCONFIG_ARCH_SUPPORTS_ATOMIC_RMW[0m
select [31mCONFIG_ARCH_SUPPORTS_NUMA_BALANCING[0m
select [31mCONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION[0m
select [31mCONFIG_ARCH_WANT_FRAME_POINTERS[0m
select [31mCONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL[0m
select [31mCONFIG_ARM_AMBA[0m
select [31mCONFIG_ARM_ARCH_TIMER[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_AUDIT_ARCH_COMPAT_GENERIC[0m
select [31mCONFIG_ARM_GIC_V2M[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_GIC_V3[0m
select [31mCONFIG_ARM_GIC_V3_ITS[0m if [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_PSCI_FW[0m
select [31mCONFIG_BUILDTIME_EXTABLE_SORT[0m
select [31mCONFIG_CLONE_BACKWARDS[0m
select [31mCONFIG_COMMON_CLK[0m
select [31mCONFIG_CPU_PM[0m if ([31mCONFIG_SUSPEND[0m || [31mCONFIG_CPU_IDLE[0m)
select [31mCONFIG_DCACHE_WORD_ACCESS[0m
select [31mCONFIG_EDAC_SUPPORT[0m
select [31mCONFIG_FRAME_POINTER[0m
select [31mCONFIG_GENERIC_ALLOCATOR[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_GENERIC_CLOCKEVENTS_BROADCAST[0m
select [31mCONFIG_GENERIC_CPU_AUTOPROBE[0m
select [31mCONFIG_GENERIC_EARLY_IOREMAP[0m
select [31mCONFIG_GENERIC_IDLE_POLL_SETUP[0m
select [31mCONFIG_GENERIC_IRQ_PROBE[0m
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_GENERIC_IRQ_SHOW_LEVEL[0m
select [31mCONFIG_GENERIC_PCI_IOMAP[0m
select [31mCONFIG_GENERIC_SCHED_CLOCK[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
select [31mCONFIG_GENERIC_STRNCPY_FROM_USER[0m
select [31mCONFIG_GENERIC_STRNLEN_USER[0m
select [31mCONFIG_GENERIC_TIME_VSYSCALL[0m
select [31mCONFIG_HANDLE_DOMAIN_IRQ[0m
select [31mCONFIG_HARDIRQS_SW_RESEND[0m
select [31mCONFIG_HAVE_ACPI_APEI[0m if ([31mCONFIG_ACPI[0m && [31mCONFIG_EFI[0m)
select [31mCONFIG_HAVE_ALIGNED_STRUCT_PAGE[0m if [31mCONFIG_SLUB[0m
select [31mCONFIG_HAVE_ARCH_AUDITSYSCALL[0m
select [31mCONFIG_HAVE_ARCH_BITREVERSE[0m
select [31mCONFIG_HAVE_ARCH_HARDENED_USERCOPY[0m
select [31mCONFIG_HAVE_ARCH_HUGE_VMAP[0m
select [31mCONFIG_HAVE_ARCH_JUMP_LABEL[0m
select [31mCONFIG_HAVE_ARCH_KASAN[0m if [31mCONFIG_SPARSEMEM_VMEMMAP[0m && !([31mCONFIG_ARM64_16K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_48[0m)
select [31mCONFIG_HAVE_ARCH_KGDB[0m
select [31mCONFIG_HAVE_ARCH_MMAP_RND_BITS[0m
select [31mCONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS[0m if [31mCONFIG_COMPAT[0m
select [31mCONFIG_HAVE_ARCH_SECCOMP_FILTER[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE[0m
select [31mCONFIG_HAVE_ARM_SMCCC[0m
select [31mCONFIG_HAVE_EBPF_JIT[0m
select [31mCONFIG_HAVE_C_RECORDMCOUNT[0m
select [31mCONFIG_HAVE_CC_STACKPROTECTOR[0m
select [31mCONFIG_HAVE_CMPXCHG_DOUBLE[0m
select [31mCONFIG_HAVE_CMPXCHG_LOCAL[0m
select [31mCONFIG_HAVE_CONTEXT_TRACKING[0m
select [31mCONFIG_HAVE_DEBUG_BUGVERBOSE[0m
select [31mCONFIG_HAVE_DEBUG_KMEMLEAK[0m
select [31mCONFIG_HAVE_DMA_API_DEBUG[0m
select [31mCONFIG_HAVE_DMA_CONTIGUOUS[0m
select [31mCONFIG_HAVE_DYNAMIC_FTRACE[0m
select [31mCONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS[0m
select [31mCONFIG_HAVE_FTRACE_MCOUNT_RECORD[0m
select [31mCONFIG_HAVE_FUNCTION_TRACER[0m
select [31mCONFIG_HAVE_FUNCTION_GRAPH_TRACER[0m
select [31mCONFIG_HAVE_GCC_PLUGINS[0m
select [31mCONFIG_HAVE_GENERIC_DMA_COHERENT[0m
select [31mCONFIG_HAVE_HW_BREAKPOINT[0m if [31mCONFIG_PERF_EVENTS[0m
select [31mCONFIG_HAVE_IRQ_TIME_ACCOUNTING[0m
select [31mCONFIG_HAVE_MEMBLOCK[0m
select [31mCONFIG_HAVE_MEMBLOCK_NODE_MAP[0m if [31mCONFIG_NUMA[0m
select [31mCONFIG_HAVE_PATA_PLATFORM[0m
select [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_HAVE_PERF_REGS[0m
select [31mCONFIG_HAVE_PERF_USER_STACK_DUMP[0m
select [31mCONFIG_HAVE_REGS_AND_STACK_ACCESS_API[0m
select [31mCONFIG_HAVE_RCU_TABLE_FREE[0m
select [31mCONFIG_HAVE_SYSCALL_TRACEPOINTS[0m
select [31mCONFIG_HAVE_KPROBES[0m
select [31mCONFIG_HAVE_KRETPROBES[0m if [31mCONFIG_HAVE_KPROBES[0m
select [31mCONFIG_IOMMU_DMA[0m if [31mCONFIG_IOMMU_SUPPORT[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_IRQ_FORCED_THREADING[0m
select [31mCONFIG_MODULES_USE_ELF_RELA[0m
select [31mCONFIG_NO_BOOTMEM[0m
select [31mCONFIG_OF[0m
select [31mCONFIG_OF_EARLY_FLATTREE[0m
select [31mCONFIG_OF_RESERVED_MEM[0m
select [31mCONFIG_PCI_ECAM[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_POWER_RESET[0m
select [31mCONFIG_POWER_SUPPLY[0m
select [31mCONFIG_SPARSE_IRQ[0m
select [31mCONFIG_SYSCTL_EXCEPTION_TRACE[0m
select [31mCONFIG_THREAD_INFO_IN_TASK[0m
help
[31mCONFIG_ARM[0m 64-bit (AArch64) Linux support.
config [31mCONFIG_64BIT[0m
def_bool y
config [31mCONFIG_ARCH_PHYS_ADDR_T_64BIT[0m
def_bool y
config [31mCONFIG_MMU[0m
def_bool y
config [31mCONFIG_DEBUG_RODATA[0m
def_bool y
config [31mCONFIG_ARM64_PAGE_SHIFT[0m
int
default 16 if [31mCONFIG_ARM64_64K_PAGES[0m
default 14 if [31mCONFIG_ARM64_16K_PAGES[0m
default 12
config [31mCONFIG_ARM64_CONT_SHIFT[0m
int
default 5 if [31mCONFIG_ARM64_64K_PAGES[0m
default 7 if [31mCONFIG_ARM64_16K_PAGES[0m
default 4
config [31mCONFIG_ARCH_MMAP_RND_BITS_MIN[0m
default 14 if [31mCONFIG_ARM64_64K_PAGES[0m
default 16 if [31mCONFIG_ARM64_16K_PAGES[0m
default 18
# max bits determined by the following formula:
# [31mCONFIG_VA_BITS[0m - PAGE_SHIFT - 3
config [31mCONFIG_ARCH_MMAP_RND_BITS_MAX[0m
default 19 if [31mCONFIG_ARM64_VA_BITS[0m=36
default 24 if [31mCONFIG_ARM64_VA_BITS[0m=39
default 27 if [31mCONFIG_ARM64_VA_BITS[0m=42
default 30 if [31mCONFIG_ARM64_VA_BITS[0m=47
default 29 if [31mCONFIG_ARM64_VA_BITS[0m=48 && [31mCONFIG_ARM64_64K_PAGES[0m
default 31 if [31mCONFIG_ARM64_VA_BITS[0m=48 && [31mCONFIG_ARM64_16K_PAGES[0m
default 33 if [31mCONFIG_ARM64_VA_BITS[0m=48
default 14 if [31mCONFIG_ARM64_64K_PAGES[0m
default 16 if [31mCONFIG_ARM64_16K_PAGES[0m
default 18
config [31mCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN[0m
default 7 if [31mCONFIG_ARM64_64K_PAGES[0m
default 9 if [31mCONFIG_ARM64_16K_PAGES[0m
default 11
config [31mCONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX[0m
default 16
config [31mCONFIG_NO_IOPORT_MAP[0m
def_bool y if ![31mCONFIG_PCI[0m
config [31mCONFIG_STACKTRACE_SUPPORT[0m
def_bool y
config [31mCONFIG_ILLEGAL_POINTER_VALUE[0m
hex
default 0xdead000000000000
config [31mCONFIG_LOCKDEP_SUPPORT[0m
def_bool y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
def_bool y
config [31mCONFIG_RWSEM_XCHGADD_ALGORITHM[0m
def_bool y
config [31mCONFIG_GENERIC_BUG[0m
def_bool y
depends on [31mCONFIG_BUG[0m
config [31mCONFIG_GENERIC_BUG_RELATIVE_POINTERS[0m
def_bool y
depends on [31mCONFIG_GENERIC_BUG[0m
config [31mCONFIG_GENERIC_HWEIGHT[0m
def_bool y
config [31mCONFIG_GENERIC_CSUM[0m
def_bool y
config [31mCONFIG_GENERIC_CALIBRATE_DELAY[0m
def_bool y
config [31mCONFIG_ZONE_DMA[0m
def_bool y
config [31mCONFIG_HAVE_GENERIC_RCU_GUP[0m
def_bool y
config [31mCONFIG_ARCH_DMA_ADDR_T_64BIT[0m
def_bool y
config [31mCONFIG_NEED_DMA_MAP_STATE[0m
def_bool y
config [31mCONFIG_NEED_SG_DMA_LENGTH[0m
def_bool y
config [31mCONFIG_SMP[0m
def_bool y
config [31mCONFIG_SWIOTLB[0m
def_bool y
config [31mCONFIG_IOMMU_HELPER[0m
def_bool [31mCONFIG_SWIOTLB[0m
config [31mCONFIG_KERNEL_MODE_NEON[0m
def_bool y
config [31mCONFIG_FIX_EARLYCON_MEM[0m
def_bool y
config [31mCONFIG_PGTABLE_LEVELS[0m
int
default 2 if [31mCONFIG_ARM64_16K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_36[0m
default 2 if [31mCONFIG_ARM64_64K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_42[0m
default 3 if [31mCONFIG_ARM64_64K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_48[0m
default 3 if [31mCONFIG_ARM64_4K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_39[0m
default 3 if [31mCONFIG_ARM64_16K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_47[0m
default 4 if ![31mCONFIG_ARM64_64K_PAGES[0m && [31mCONFIG_ARM64_VA_BITS_48[0m
config [31mCONFIG_ARCH_SUPPORTS_UPROBES[0m
def_bool y
source "init/Kconfig"
source "kernel/Kconfig.freezer"
source "arch/arm64/Kconfig.platforms"
menu "Bus support"
config [31mCONFIG_PCI[0m
bool "PCI support"
help
This feature enables support for [31mCONFIG_PCI[0m bus system. If you say Y
here, the kernel will include drivers and infrastructure code
to support [31mCONFIG_PCI[0m bus devices.
config [31mCONFIG_PCI_DOMAINS[0m
def_bool [31mCONFIG_PCI[0m
config [31mCONFIG_PCI_DOMAINS_GENERIC[0m
def_bool [31mCONFIG_PCI[0m
config [31mCONFIG_PCI_SYSCALL[0m
def_bool [31mCONFIG_PCI[0m
source "drivers/pci/Kconfig"
endmenu
menu "Kernel Features"
menu "ARM errata workarounds via the alternatives framework"
config [31mCONFIG_ARM64_ERRATUM_826319[0m
bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
AXI master interface and an L2 cache.
If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
and is unable to accept a certain write via this interface, it will
not progress on read data presented on the read data channel and the
system can deadlock.
The workaround promotes data cache clean instructions to
data cache clean-and-invalidate.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_827319[0m
bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
master interface and an L2 cache.
Under certain conditions this erratum can cause a clean line eviction
to occur at the same time as another transaction to the same address
on the AMBA 5 CHI interface, which can cause data corruption if the
interconnect reorders the two transactions.
The workaround promotes data cache clean instructions to
data cache clean-and-invalidate.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_824069[0m
bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
to a coherent interconnect.
If a Cortex-A53 processor is executing a store or prefetch for
write instruction at the same time as a processor in another
cluster is executing a cache maintenance operation to the same
address, then this erratum might cause a clean cache line to be
incorrectly marked as dirty.
The workaround promotes data cache clean instructions to
data cache clean-and-invalidate.
Please note that this option does not necessarily enable the
workaround, as it depends on the alternative framework, which will
only patch the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_819472[0m
bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
present when it is connected to a coherent interconnect.
If the processor is executing a load and store exclusive sequence at
the same time as a processor in another cluster is executing a cache
maintenance operation to the same address, then this erratum might
cause data corruption.
The workaround promotes data cache clean instructions to
data cache clean-and-invalidate.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_832075[0m
bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 832075 on Cortex-A57 parts up to r1p2.
Affected Cortex-A57 parts might deadlock when exclusive load/store
instructions to Write-Back memory are mixed with Device loads.
The workaround is to promote device loads to use Load-Acquire
semantics.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_834220[0m
bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
depends on [31mCONFIG_KVM[0m
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 834220 on Cortex-A57 parts up to r1p2.
Affected Cortex-A57 parts might report a Stage 2 translation
fault as the result of a Stage 1 fault for load crossing a
page boundary when there is a permission or device memory
alignment fault at Stage 1 and a translation fault at Stage 2.
The workaround is to verify that the Stage 1 translation
doesn't generate a fault before handling the Stage 2 fault.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_845719[0m
bool "Cortex-A53: 845719: a load might read incorrect data"
depends on [31mCONFIG_COMPAT[0m
default y
help
This option adds an alternative code sequence to work around [31mCONFIG_ARM[0m
erratum 845719 on Cortex-A53 parts up to r0p4.
When running a compat (AArch32) userspace on an affected Cortex-A53
part, a load at EL0 from a virtual address that matches the bottom 32
bits of the virtual address used by a recent load at (AArch64) EL1
might return incorrect data.
The workaround is to write the contextidr_el1 register on exception
return to a 32-bit task.
Please note that this does not necessarily enable the workaround,
as it depends on the alternative framework, which will only patch
the kernel if an affected CPU is detected.
If unsure, say Y.
config [31mCONFIG_ARM64_ERRATUM_843419[0m
bool "Cortex-A53: 843419: A load or store might access an incorrect address"
default y
select [31mCONFIG_ARM64_MODULE_CMODEL_LARGE[0m if [31mCONFIG_MODULES[0m
help
This option links the kernel with '--fix-cortex-a53-843419' and
builds modules using the large memory model in order to avoid the use
of the ADRP instruction, which can cause a subsequent memory access
to use an incorrect address on Cortex-A53 parts up to r0p4.
If unsure, say Y.
config [31mCONFIG_CAVIUM_ERRATUM_22375[0m
bool "Cavium erratum 22375, 24313"
default y
help
Enable workaround for erratum 22375, 24313.
This implements two gicv3-its errata workarounds for ThunderX. Both
with small impact affecting only ITS table allocation.
erratum 22375: only alloc 8MB table size
erratum 24313: ignore memory access type
The fixes are in ITS initialization and basically ignore memory access
type and table size provided by the TYPER and BASER registers.
If unsure, say Y.
config [31mCONFIG_CAVIUM_ERRATUM_23144[0m
bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
depends on [31mCONFIG_NUMA[0m
default y
help
ITS SYNC command hang for cross node io and collections/cpu mapping.
If unsure, say Y.
config [31mCONFIG_CAVIUM_ERRATUM_23154[0m
bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
default y
help
The gicv3 of ThunderX requires a modified version for
reading the IAR status to ensure data synchronization
(access to icc_iar1_el1 is not sync'ed before and after).
If unsure, say Y.
config [31mCONFIG_CAVIUM_ERRATUM_27456[0m
bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
default y
help
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it
contains data for a non-current ASID. The fix is to
invalidate the icache when changing the mm context.
If unsure, say Y.
endmenu
choice
prompt "Page size"
default [31mCONFIG_ARM64_4K_PAGES[0m
help
Page size (translation granule) configuration.
config [31mCONFIG_ARM64_4K_PAGES[0m
bool "4KB"
help
This feature enables 4KB pages support.
config [31mCONFIG_ARM64_16K_PAGES[0m
bool "16KB"
help
The system will use 16KB pages support. AArch32 emulation
requires applications compiled with 16K (or a multiple of 16K)
aligned segments.
config [31mCONFIG_ARM64_64K_PAGES[0m
bool "64KB"
help
This feature enables 64KB pages support (4KB by default)
allowing only two levels of page tables and faster TLB
look-up. AArch32 emulation requires applications compiled
with 64K aligned segments.
endchoice
choice
prompt "Virtual address space size"
default [31mCONFIG_ARM64_VA_BITS_39[0m if [31mCONFIG_ARM64_4K_PAGES[0m
default [31mCONFIG_ARM64_VA_BITS_47[0m if [31mCONFIG_ARM64_16K_PAGES[0m
default [31mCONFIG_ARM64_VA_BITS_42[0m if [31mCONFIG_ARM64_64K_PAGES[0m
help
Allows choosing one of multiple possible virtual address
space sizes. The level of translation table is determined by
a combination of page size and virtual address space size.
config [31mCONFIG_ARM64_VA_BITS_36[0m
bool "36-bit" if [31mCONFIG_EXPERT[0m
depends on [31mCONFIG_ARM64_16K_PAGES[0m
config [31mCONFIG_ARM64_VA_BITS_39[0m
bool "39-bit"
depends on [31mCONFIG_ARM64_4K_PAGES[0m
config [31mCONFIG_ARM64_VA_BITS_42[0m
bool "42-bit"
depends on [31mCONFIG_ARM64_64K_PAGES[0m
config [31mCONFIG_ARM64_VA_BITS_47[0m
bool "47-bit"
depends on [31mCONFIG_ARM64_16K_PAGES[0m
config [31mCONFIG_ARM64_VA_BITS_48[0m
bool "48-bit"
endchoice
config [31mCONFIG_ARM64_VA_BITS[0m
int
default 36 if [31mCONFIG_ARM64_VA_BITS_36[0m
default 39 if [31mCONFIG_ARM64_VA_BITS_39[0m
default 42 if [31mCONFIG_ARM64_VA_BITS_42[0m
default 47 if [31mCONFIG_ARM64_VA_BITS_47[0m
default 48 if [31mCONFIG_ARM64_VA_BITS_48[0m
config [31mCONFIG_CPU_BIG_ENDIAN[0m
bool "Build big-endian kernel"
help
Say Y if you plan on running a kernel in big-endian mode.
config [31mCONFIG_SCHED_MC[0m
bool "Multi-core scheduler support"
help
Multi-core scheduler support improves the CPU scheduler's decision
making when dealing with multi-core CPU chips at a cost of slightly
increased overhead in some places. If unsure say N here.
config [31mCONFIG_SCHED_SMT[0m
bool "SMT scheduler support"
help
Improves the CPU scheduler's decision making when dealing with
MultiThreading at a cost of slightly increased overhead in some
places. If unsure say N here.
config [31mCONFIG_NR_CPUS[0m
int "Maximum number of CPUs (2-4096)"
range 2 4096
# These have to remain sorted largest to smallest
default "64"
config [31mCONFIG_HOTPLUG_CPU[0m
bool "Support for hot-pluggable CPUs"
select [31mCONFIG_GENERIC_IRQ_MIGRATION[0m
help
Say Y here to experiment with turning CPUs off and on. CPUs
can be controlled through /sys/devices/system/cpu.
# Common [31mCONFIG_NUMA[0m Features
config [31mCONFIG_NUMA[0m
bool "Numa Memory Allocation and Scheduler Support"
select [31mCONFIG_ACPI_NUMA[0m if [31mCONFIG_ACPI[0m
select [31mCONFIG_OF_NUMA[0m
help
Enable [31mCONFIG_NUMA[0m (Non Uniform Memory Access) support.
The kernel will try to allocate memory used by a CPU on the
local memory of the CPU and add some more
[31mCONFIG_NUMA[0m awareness to the kernel.
config [31mCONFIG_NODES_SHIFT[0m
int "Maximum NUMA Nodes (as a power of 2)"
range 1 10
default "2"
depends on [31mCONFIG_NEED_MULTIPLE_NODES[0m
help
Specify the maximum number of [31mCONFIG_NUMA[0m Nodes available on the target
system. Increases memory reserved to accommodate various tables.
config [31mCONFIG_USE_PERCPU_NUMA_NODE_ID[0m
def_bool y
depends on [31mCONFIG_NUMA[0m
config [31mCONFIG_HAVE_SETUP_PER_CPU_AREA[0m
def_bool y
depends on [31mCONFIG_NUMA[0m
config [31mCONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK[0m
def_bool y
depends on [31mCONFIG_NUMA[0m
source kernel/Kconfig.preempt
source kernel/Kconfig.hz
config [31mCONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC[0m
def_bool y
config [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m
def_bool y if [31mCONFIG_SPARSEMEM[0m
config [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
def_bool y
select [31mCONFIG_SPARSEMEM_VMEMMAP_ENABLE[0m
config [31mCONFIG_ARCH_SPARSEMEM_DEFAULT[0m
def_bool [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
config [31mCONFIG_ARCH_SELECT_MEMORY_MODEL[0m
def_bool [31mCONFIG_ARCH_SPARSEMEM_ENABLE[0m
config [31mCONFIG_HAVE_ARCH_PFN_VALID[0m
def_bool [31mCONFIG_ARCH_HAS_HOLES_MEMORYMODEL[0m || ![31mCONFIG_SPARSEMEM[0m
config [31mCONFIG_HW_PERF_EVENTS[0m
def_bool y
depends on [31mCONFIG_ARM_PMU[0m
config [31mCONFIG_SYS_SUPPORTS_HUGETLBFS[0m
def_bool y
config [31mCONFIG_ARCH_WANT_HUGE_PMD_SHARE[0m
def_bool y if [31mCONFIG_ARM64_4K_PAGES[0m || ([31mCONFIG_ARM64_16K_PAGES[0m && ![31mCONFIG_ARM64_VA_BITS_36[0m)
config [31mCONFIG_ARCH_HAS_CACHE_LINE_SIZE[0m
def_bool y
source "mm/Kconfig"
config [31mCONFIG_SECCOMP[0m
bool "Enable seccomp to safely compute untrusted bytecode"
---help---
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
config [31mCONFIG_PARAVIRT[0m
bool "Enable paravirtualization code"
help
This changes the kernel so it can modify itself when it is run
under a hypervisor, potentially improving performance significantly
over full virtualization.
config [31mCONFIG_PARAVIRT_TIME_ACCOUNTING[0m
bool "Paravirtual steal time accounting"
select [31mCONFIG_PARAVIRT[0m
default n
help
Select this option to enable fine granularity task steal time
accounting. Time spent executing other tasks in parallel with
the current vCPU is discounted from the vCPU power. To account for
that, there can be a small performance impact.
If in doubt, say N here.
config [31mCONFIG_KEXEC[0m
depends on [31mCONFIG_PM_SLEEP_SMP[0m
select [31mCONFIG_KEXEC_CORE[0m
bool "kexec system call"
---help---
kexec is a system call that implements the ability to shutdown your
current kernel, and to start another kernel. It is like a reboot
but it is independent of the system firmware. And like a reboot
you can start any kernel with it, not just Linux.
config [31mCONFIG_XEN_DOM0[0m
def_bool y
depends on [31mCONFIG_XEN[0m
config [31mCONFIG_XEN[0m
bool "Xen guest support on ARM64"
depends on [31mCONFIG_ARM64[0m && [31mCONFIG_OF[0m
select [31mCONFIG_SWIOTLB_XEN[0m
select [31mCONFIG_PARAVIRT[0m
help
Say Y if you want to run Linux in a Virtual Machine on Xen on [31mCONFIG_ARM64[0m.
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int
default "14" if ([31mCONFIG_ARM64_64K_PAGES[0m && [31mCONFIG_TRANSPARENT_HUGEPAGE[0m)
default "12" if ([31mCONFIG_ARM64_16K_PAGES[0m && [31mCONFIG_TRANSPARENT_HUGEPAGE[0m)
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
We make sure that we can allocate upto a HugePage size for each configuration.
Hence we have :
MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
4M allocations matching the default size used by generic code.
menuconfig [31mCONFIG_ARMV8_DEPRECATED[0m
bool "Emulate deprecated/obsolete ARMv8 instructions"
depends on [31mCONFIG_COMPAT[0m
help
Legacy software support may require certain instructions
that have been deprecated or obsoleted in the architecture.
Enable this config to enable selective emulation of these
features.
If unsure, say Y
if [31mCONFIG_ARMV8_DEPRECATED[0m
config [31mCONFIG_SWP_EMULATION[0m
bool "Emulate SWP/SWPB instructions"
help
ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
they are always undefined. Say Y here to enable software
emulation of these instructions for userspace using LDXR/STXR.
In some older versions of glibc [<=2.8] SWP is used during futex
trylock() operations with the assumption that the code will not
be preempted. This invalid assumption may be more likely to fail
with SWP emulation enabled, leading to deadlock of the user
application.
NOTE: when accessing uncached shared regions, LDXR/STXR rely
on an external transaction monitoring block called a global
monitor to maintain update atomicity. If your system does not
implement a global monitor, this option can cause programs that
perform SWP operations to uncached memory to deadlock.
If unsure, say Y
config [31mCONFIG_CP15_BARRIER_EMULATION[0m
bool "Emulate CP15 Barrier instructions"
help
The CP15 barrier instructions - CP15ISB, CP15DSB, and
CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
strongly recommended to use the ISB, DSB, and DMB
instructions instead.
Say Y here to enable software emulation of these
instructions for AArch32 userspace code. When this option is
enabled, CP15 barrier usage is traced which can help
identify software that needs updating.
If unsure, say Y
config [31mCONFIG_SETEND_EMULATION[0m
bool "Emulate SETEND instruction"
help
The SETEND instruction alters the data-endianness of the
AArch32 EL0, and is deprecated in ARMv8.
Say Y here to enable software emulation of the instruction
for AArch32 userspace code.
Note: All the cpus on the system must have mixed endian support at EL0
for this feature to be enabled. If a new CPU - which doesn't support mixed
endian - is hotplugged in after this feature has been enabled, there could
be unexpected results in the applications.
If unsure, say Y
endif
config [31mCONFIG_ARM64_SW_TTBR0_PAN[0m
bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
help
Enabling this option prevents the kernel from accessing
user-space memory directly by pointing TTBR0_EL1 to a reserved
zeroed area and reserved ASID. The user access routines
restore the valid TTBR0_EL1 temporarily.
menu "ARMv8.1 architectural features"
config [31mCONFIG_ARM64_HW_AFDBM[0m
bool "Support for hardware updates of the Access and Dirty page flags"
default y
help
The ARMv8.1 architecture extensions introduce support for
hardware updates of the access and dirty information in page
table entries. When enabled in TCR_EL1 (HA and HD bits) on
capable processors, accesses to pages with PTE_AF cleared will
set this bit instead of raising an access flag fault.
Similarly, writes to read-only pages with the DBM bit set will
clear the read-only bit (AP[2]) instead of raising a
permission fault.
Kernels built with this configuration option enabled continue
to work on pre-ARMv8.1 hardware and the performance impact is
minimal. If unsure, say Y.
config [31mCONFIG_ARM64_PAN[0m
bool "Enable support for Privileged Access Never (PAN)"
default y
help
Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
prevents the kernel or hypervisor from accessing user-space (EL0)
memory directly.
Choosing this option will cause any unprotected (not using
copy_to_user et al) memory access to fail with a permission fault.
The feature is detected at runtime, and will remain as a 'nop'
instruction if the cpu does not implement the feature.
config [31mCONFIG_ARM64_LSE_ATOMICS[0m
bool "Atomic instructions"
help
As part of the Large System Extensions, ARMv8.1 introduces new
atomic instructions that are designed specifically to scale in
very large systems.
Say Y here to make use of these instructions for the in-kernel
atomic routines. This incurs a small overhead on CPUs that do
not support these instructions and requires the kernel to be
built with binutils >= 2.25.
config [31mCONFIG_ARM64_VHE[0m
bool "Enable support for Virtualization Host Extensions (VHE)"
default y
help
Virtualization Host Extensions (VHE) allow the kernel to run
directly at EL2 (instead of EL1) on processors that support
it. This leads to better performance for [31mCONFIG_KVM[0m, as they reduce
the cost of the world switch.
Selecting this option allows the VHE feature to be detected
at runtime, and does not affect processors that do not
implement this feature.
endmenu
menu "ARMv8.2 architectural features"
config [31mCONFIG_ARM64_UAO[0m
bool "Enable support for User Access Override (UAO)"
default y
help
User Access Override (UAO; part of the ARMv8.2 Extensions)
causes the 'unprivileged' variant of the load/store instructions to
be overriden to be privileged.
This option changes get_user() and friends to use the 'unprivileged'
variant of the load/store instructions. This ensures that user-space
really did have access to the supplied memory. When addr_limit is
set to kernel memory the UAO bit will be set, allowing privileged
access to kernel memory.
Choosing this option will cause copy_to_user() et al to use user-space
memory permissions.
The feature is detected at runtime, the kernel will use the
regular load/store instructions if the cpu does not implement the
feature.
endmenu
config [31mCONFIG_ARM64_MODULE_CMODEL_LARGE[0m
bool
config [31mCONFIG_ARM64_MODULE_PLTS[0m
bool
select [31mCONFIG_ARM64_MODULE_CMODEL_LARGE[0m
select [31mCONFIG_HAVE_MOD_ARCH_SPECIFIC[0m
config [31mCONFIG_RELOCATABLE[0m
bool
help
This builds the kernel as a Position Independent Executable (PIE),
which retains all relocation metadata required to relocate the
kernel binary at runtime to a different virtual address than the
address it was linked at.
Since AArch64 uses the RELA relocation format, this requires a
relocation pass at runtime even if the kernel is loaded at the
same address it was linked at.
config [31mCONFIG_RANDOMIZE_BASE[0m
bool "Randomize the address of the kernel image"
select [31mCONFIG_ARM64_MODULE_PLTS[0m if [31mCONFIG_MODULES[0m
select [31mCONFIG_RELOCATABLE[0m
help
Randomizes the virtual address at which the kernel image is
loaded, as a security feature that deters exploit attempts
relying on knowledge of the location of kernel internals.
It is the bootloader's job to provide entropy, by passing a
random u64 value in /chosen/kaslr-seed at kernel entry.
When booting via the UEFI stub, it will invoke the firmware's
EFI_RNG_PROTOCOL implementation (if available) to supply entropy
to the kernel proper. In addition, it will randomise the physical
location of the kernel Image as well.
If unsure, say N.
config [31mCONFIG_RANDOMIZE_MODULE_REGION_FULL[0m
bool "Randomize the module region independently from the core kernel"
depends on [31mCONFIG_RANDOMIZE_BASE[0m && ![31mCONFIG_DYNAMIC_FTRACE[0m
default y
help
Randomizes the location of the module region without considering the
location of the core kernel. This way, it is impossible for modules
to leak information about the location of core kernel data structures
but it does imply that function calls between modules and the core
kernel will need to be resolved via veneers in the module PLT.
When this option is not set, the module region will be randomized over
a limited range that contains the [_stext, _etext] interval of the
core kernel, so branch relocations are always in range.
endmenu
menu "Boot options"
config [31mCONFIG_ARM64_ACPI_PARKING_PROTOCOL[0m
bool "Enable support for the ARM64 ACPI parking protocol"
depends on [31mCONFIG_ACPI[0m
help
Enable support for the [31mCONFIG_ARM64[0m [31mCONFIG_ACPI[0m parking protocol. If disabled
the kernel will not allow booting through the [31mCONFIG_ARM64[0m [31mCONFIG_ACPI[0m parking
protocol even if the corresponding data is present in the [31mCONFIG_ACPI[0m
MADT table.
config [31mCONFIG_CMDLINE[0m
string "Default kernel command string"
default ""
help
Provide a set of default command-line options at build time by
entering them here. As a minimum, you should specify the the
root device (e.g. root=/dev/nfs).
config [31mCONFIG_CMDLINE_FORCE[0m
bool "Always use the default kernel command string"
help
Always use the default kernel command string, even if the boot
loader passes other arguments to the kernel.
This is useful if you cannot or don't want to change the
command-line options your boot loader passes to the kernel.
config [31mCONFIG_EFI_STUB[0m
bool
config [31mCONFIG_EFI[0m
bool "UEFI runtime support"
depends on [31mCONFIG_OF[0m && ![31mCONFIG_CPU_BIG_ENDIAN[0m
select [31mCONFIG_LIBFDT[0m
select [31mCONFIG_UCS2_STRING[0m
select [31mCONFIG_EFI_PARAMS_FROM_FDT[0m
select [31mCONFIG_EFI_RUNTIME_WRAPPERS[0m
select [31mCONFIG_EFI_STUB[0m
select [31mCONFIG_EFI_ARMSTUB[0m
default y
help
This option provides support for runtime services provided
by UEFI firmware (such as non-volatile variables, realtime
clock, and platform reset). [31mCONFIG_A[0m UEFI stub is also provided to
allow the kernel to be booted as an [31mCONFIG_EFI[0m application. This
is only useful on systems that have UEFI firmware.
config [31mCONFIG_DMI[0m
bool "Enable support for SMBIOS (DMI) tables"
depends on [31mCONFIG_EFI[0m
default y
help
This enables SMBIOS/[31mCONFIG_DMI[0m feature for systems.
This option is only useful on systems that have UEFI firmware.
However, even with this option, the resultant kernel should
continue to boot on existing non-UEFI platforms.
endmenu
menu "Userspace binary formats"
source "fs/Kconfig.binfmt"
config [31mCONFIG_COMPAT[0m
bool "Kernel support for 32-bit EL0"
depends on [31mCONFIG_ARM64_4K_PAGES[0m || [31mCONFIG_EXPERT[0m
select [31mCONFIG_COMPAT_BINFMT_ELF[0m
select [31mCONFIG_HAVE_UID16[0m
select [31mCONFIG_OLD_SIGSUSPEND3[0m
select [31mCONFIG_COMPAT_OLD_SIGACTION[0m
help
This option enables support for a 32-bit EL0 running under a 64-bit
kernel at EL1. AArch32-specific components such as system calls,
the user helper functions, [31mCONFIG_VFP[0m support and the ptrace interface are
handled appropriately by the kernel.
If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
that you will only be able to execute AArch32 binaries that were compiled
with page size aligned segments.
If you want to execute 32-bit userspace applications, say Y.
config [31mCONFIG_SYSVIPC_COMPAT[0m
def_bool y
depends on [31mCONFIG_COMPAT[0m && [31mCONFIG_SYSVIPC[0m
endmenu
menu "Power management options"
source "kernel/power/Kconfig"
config [31mCONFIG_ARCH_HIBERNATION_POSSIBLE[0m
def_bool y
depends on [31mCONFIG_CPU_PM[0m
config [31mCONFIG_ARCH_HIBERNATION_HEADER[0m
def_bool y
depends on [31mCONFIG_HIBERNATION[0m
config [31mCONFIG_ARCH_SUSPEND_POSSIBLE[0m
def_bool y
endmenu
menu "CPU Power Management"
source "drivers/cpuidle/Kconfig"
source "drivers/cpufreq/Kconfig"
endmenu
source "net/Kconfig"
source "drivers/Kconfig"
source "drivers/firmware/Kconfig"
source "drivers/acpi/Kconfig"
source "fs/Kconfig"
source "arch/arm64/kvm/Kconfig"
source "arch/arm64/Kconfig.debug"
source "security/Kconfig"
source "crypto/Kconfig"
if [31mCONFIG_CRYPTO[0m
source "arch/arm64/crypto/Kconfig"
endif
source "lib/Kconfig"