config [31mCONFIG_MMU[0m
def_bool n
config [31mCONFIG_FPU[0m
def_bool n
config [31mCONFIG_RWSEM_GENERIC_SPINLOCK[0m
def_bool y
config [31mCONFIG_RWSEM_XCHGADD_ALGORITHM[0m
def_bool n
config [31mCONFIG_BLACKFIN[0m
def_bool y
select [31mCONFIG_HAVE_ARCH_KGDB[0m
select [31mCONFIG_HAVE_ARCH_TRACEHOOK[0m
select [31mCONFIG_HAVE_DYNAMIC_FTRACE[0m
select [31mCONFIG_HAVE_FTRACE_MCOUNT_RECORD[0m
select [31mCONFIG_HAVE_FUNCTION_GRAPH_TRACER[0m
select [31mCONFIG_HAVE_FUNCTION_TRACER[0m
select [31mCONFIG_HAVE_IDE[0m
select [31mCONFIG_HAVE_KERNEL_GZIP[0m if [31mCONFIG_RAMKERNEL[0m
select [31mCONFIG_HAVE_KERNEL_BZIP2[0m if [31mCONFIG_RAMKERNEL[0m
select [31mCONFIG_HAVE_KERNEL_LZMA[0m if [31mCONFIG_RAMKERNEL[0m
select [31mCONFIG_HAVE_KERNEL_LZO[0m if [31mCONFIG_RAMKERNEL[0m
select [31mCONFIG_HAVE_OPROFILE[0m
select [31mCONFIG_HAVE_PERF_EVENTS[0m
select [31mCONFIG_ARCH_HAVE_CUSTOM_GPIO_H[0m
select [31mCONFIG_GPIOLIB[0m
select [31mCONFIG_HAVE_UID16[0m
select [31mCONFIG_HAVE_UNDERSCORE_SYMBOL_PREFIX[0m
select [31mCONFIG_VIRT_TO_BUS[0m
select [31mCONFIG_ARCH_WANT_IPC_PARSE_VERSION[0m
select [31mCONFIG_GENERIC_ATOMIC64[0m
select [31mCONFIG_GENERIC_IRQ_PROBE[0m
select [31mCONFIG_GENERIC_IRQ_SHOW[0m
select [31mCONFIG_HAVE_NMI_WATCHDOG[0m if [31mCONFIG_NMI_WATCHDOG[0m
select [31mCONFIG_GENERIC_SMP_IDLE_THREAD[0m
select [31mCONFIG_ARCH_USES_GETTIMEOFFSET[0m if ![31mCONFIG_GENERIC_CLOCKEVENTS[0m
select [31mCONFIG_HAVE_MOD_ARCH_SPECIFIC[0m
select [31mCONFIG_MODULES_USE_ELF_RELA[0m
select [31mCONFIG_HAVE_DEBUG_STACKOVERFLOW[0m
select [31mCONFIG_HAVE_NMI[0m
config [31mCONFIG_GENERIC_CSUM[0m
def_bool y
config [31mCONFIG_GENERIC_BUG[0m
def_bool y
depends on [31mCONFIG_BUG[0m
config [31mCONFIG_ZONE_DMA[0m
def_bool y
config [31mCONFIG_FORCE_MAX_ZONEORDER[0m
int
default "14"
config [31mCONFIG_GENERIC_CALIBRATE_DELAY[0m
def_bool y
config [31mCONFIG_LOCKDEP_SUPPORT[0m
def_bool y
config [31mCONFIG_STACKTRACE_SUPPORT[0m
def_bool y
config [31mCONFIG_TRACE_IRQFLAGS_SUPPORT[0m
def_bool y
source "init/Kconfig"
source "kernel/Kconfig.preempt"
source "kernel/Kconfig.freezer"
menu "Blackfin Processor Options"
comment "Processor and Board Settings"
choice
prompt "CPU"
default [31mCONFIG_BF533[0m
config [31mCONFIG_BF512[0m
bool "BF512"
help
[31mCONFIG_BF512[0m Processor Support.
config [31mCONFIG_BF514[0m
bool "BF514"
help
[31mCONFIG_BF514[0m Processor Support.
config [31mCONFIG_BF516[0m
bool "BF516"
help
[31mCONFIG_BF516[0m Processor Support.
config [31mCONFIG_BF518[0m
bool "BF518"
help
[31mCONFIG_BF518[0m Processor Support.
config [31mCONFIG_BF522[0m
bool "BF522"
help
[31mCONFIG_BF522[0m Processor Support.
config [31mCONFIG_BF523[0m
bool "BF523"
help
[31mCONFIG_BF523[0m Processor Support.
config [31mCONFIG_BF524[0m
bool "BF524"
help
[31mCONFIG_BF524[0m Processor Support.
config [31mCONFIG_BF525[0m
bool "BF525"
help
[31mCONFIG_BF525[0m Processor Support.
config [31mCONFIG_BF526[0m
bool "BF526"
help
[31mCONFIG_BF526[0m Processor Support.
config [31mCONFIG_BF527[0m
bool "BF527"
help
[31mCONFIG_BF527[0m Processor Support.
config [31mCONFIG_BF531[0m
bool "BF531"
help
[31mCONFIG_BF531[0m Processor Support.
config [31mCONFIG_BF532[0m
bool "BF532"
help
[31mCONFIG_BF532[0m Processor Support.
config [31mCONFIG_BF533[0m
bool "BF533"
help
[31mCONFIG_BF533[0m Processor Support.
config [31mCONFIG_BF534[0m
bool "BF534"
help
[31mCONFIG_BF534[0m Processor Support.
config [31mCONFIG_BF536[0m
bool "BF536"
help
[31mCONFIG_BF536[0m Processor Support.
config [31mCONFIG_BF537[0m
bool "BF537"
help
[31mCONFIG_BF537[0m Processor Support.
config [31mCONFIG_BF538[0m
bool "BF538"
help
[31mCONFIG_BF538[0m Processor Support.
config [31mCONFIG_BF539[0m
bool "BF539"
help
[31mCONFIG_BF539[0m Processor Support.
config [31mCONFIG_BF542_std[0m
bool "BF542"
help
[31mCONFIG_BF542[0m Processor Support.
config [31mCONFIG_BF542M[0m
bool "BF542m"
help
[31mCONFIG_BF542[0m Processor Support.
config [31mCONFIG_BF544_std[0m
bool "BF544"
help
[31mCONFIG_BF544[0m Processor Support.
config [31mCONFIG_BF544M[0m
bool "BF544m"
help
[31mCONFIG_BF544[0m Processor Support.
config [31mCONFIG_BF547_std[0m
bool "BF547"
help
[31mCONFIG_BF547[0m Processor Support.
config [31mCONFIG_BF547M[0m
bool "BF547m"
help
[31mCONFIG_BF547[0m Processor Support.
config [31mCONFIG_BF548_std[0m
bool "BF548"
help
[31mCONFIG_BF548[0m Processor Support.
config [31mCONFIG_BF548M[0m
bool "BF548m"
help
[31mCONFIG_BF548[0m Processor Support.
config [31mCONFIG_BF549_std[0m
bool "BF549"
help
[31mCONFIG_BF549[0m Processor Support.
config [31mCONFIG_BF549M[0m
bool "BF549m"
help
[31mCONFIG_BF549[0m Processor Support.
config [31mCONFIG_BF561[0m
bool "BF561"
help
[31mCONFIG_BF561[0m Processor Support.
config [31mCONFIG_BF609[0m
bool "BF609"
select [31mCONFIG_CLKDEV_LOOKUP[0m
help
[31mCONFIG_BF609[0m Processor Support.
endchoice
config [31mCONFIG_SMP[0m
depends on [31mCONFIG_BF561[0m
select [31mCONFIG_TICKSOURCE_CORETMR[0m
bool "Symmetric multi-processing support"
---help---
This enables support for systems with more than one CPU,
like the dual core [31mCONFIG_BF561[0m. If you have a system with only one
CPU, say N. If you have a system with more than one CPU, say Y.
If you don't know what to do here, say N.
config [31mCONFIG_NR_CPUS[0m
int
depends on [31mCONFIG_SMP[0m
default 2 if [31mCONFIG_BF561[0m
config [31mCONFIG_HOTPLUG_CPU[0m
bool "Support for hot-pluggable CPUs"
depends on [31mCONFIG_SMP[0m
default y
config [31mCONFIG_BF_REV_MIN[0m
int
default 0 if ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m)) || [31mCONFIG_BF60x[0m
default 2 if ([31mCONFIG_BF537[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF534[0m)
default 3 if ([31mCONFIG_BF561[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m || [31mCONFIG_BF54xM[0m)
default 4 if ([31mCONFIG_BF538[0m || [31mCONFIG_BF539[0m)
config [31mCONFIG_BF_REV_MAX[0m
int
default 2 if ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m)) || [31mCONFIG_BF60x[0m
default 3 if ([31mCONFIG_BF537[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF534[0m || [31mCONFIG_BF54xM[0m)
default 5 if ([31mCONFIG_BF561[0m || [31mCONFIG_BF538[0m || [31mCONFIG_BF539[0m)
default 6 if ([31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m)
choice
prompt "Silicon Rev"
default [31mCONFIG_BF_REV_0_0[0m if ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || [31mCONFIG_BF60x[0m)
default [31mCONFIG_BF_REV_0_2[0m if ([31mCONFIG_BF534[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF537[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m))
default [31mCONFIG_BF_REV_0_3[0m if ([31mCONFIG_BF531[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF54xM[0m || [31mCONFIG_BF561[0m)
config [31mCONFIG_BF_REV_0_0[0m
bool "0.0"
depends on ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m) || [31mCONFIG_BF60x[0m)
config [31mCONFIG_BF_REV_0_1[0m
bool "0.1"
depends on ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m) || [31mCONFIG_BF60x[0m)
config [31mCONFIG_BF_REV_0_2[0m
bool "0.2"
depends on ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || [31mCONFIG_BF537[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF534[0m || ([31mCONFIG_BF54x[0m && ![31mCONFIG_BF54xM[0m))
config [31mCONFIG_BF_REV_0_3[0m
bool "0.3"
depends on ([31mCONFIG_BF54xM[0m || [31mCONFIG_BF561[0m || [31mCONFIG_BF537[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF534[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m)
config [31mCONFIG_BF_REV_0_4[0m
bool "0.4"
depends on ([31mCONFIG_BF561[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m || [31mCONFIG_BF538[0m || [31mCONFIG_BF539[0m || [31mCONFIG_BF54x[0m)
config [31mCONFIG_BF_REV_0_5[0m
bool "0.5"
depends on ([31mCONFIG_BF561[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m || [31mCONFIG_BF538[0m || [31mCONFIG_BF539[0m)
config [31mCONFIG_BF_REV_0_6[0m
bool "0.6"
depends on ([31mCONFIG_BF533[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF531[0m)
config [31mCONFIG_BF_REV_ANY[0m
bool "any"
config [31mCONFIG_BF_REV_NONE[0m
bool "none"
endchoice
config [31mCONFIG_BF53x[0m
bool
depends on ([31mCONFIG_BF531[0m || [31mCONFIG_BF532[0m || [31mCONFIG_BF533[0m || [31mCONFIG_BF534[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF537[0m)
default y
config [31mCONFIG_GPIO_ADI[0m
def_bool y
depends on ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || [31mCONFIG_BF53x[0m || [31mCONFIG_BF538[0m || [31mCONFIG_BF539[0m || [31mCONFIG_BF561[0m)
config [31mCONFIG_PINCTRL[0m
def_bool y
depends on [31mCONFIG_BF54x[0m || [31mCONFIG_BF60x[0m
config [31mCONFIG_MEM_MT48LC64M4A2FB_7E[0m
bool
depends on ([31mCONFIG_BFIN533_STAMP[0m)
default y
config [31mCONFIG_MEM_MT48LC16M16A2TG_75[0m
bool
depends on ([31mCONFIG_BFIN533_EZKIT[0m || [31mCONFIG_BFIN561_EZKIT[0m \
|| [31mCONFIG_BFIN533_BLUETECHNIX_CM[0m || [31mCONFIG_BFIN537_BLUETECHNIX_CM_E[0m \
|| [31mCONFIG_BFIN537_BLUETECHNIX_CM_U[0m || [31mCONFIG_H8606_HVSISTEMAS[0m \
|| [31mCONFIG_BFIN527_BLUETECHNIX_CM[0m)
default y
config [31mCONFIG_MEM_MT48LC32M8A2_75[0m
bool
depends on ([31mCONFIG_BFIN518F_EZBRD[0m || [31mCONFIG_BFIN537_STAMP[0m || [31mCONFIG_PNAV10[0m || [31mCONFIG_BFIN538_EZKIT[0m)
default y
config [31mCONFIG_MEM_MT48LC8M32B2B5_7[0m
bool
depends on ([31mCONFIG_BFIN561_BLUETECHNIX_CM[0m)
default y
config [31mCONFIG_MEM_MT48LC32M16A2TG_75[0m
bool
depends on ([31mCONFIG_BFIN527_EZKIT[0m || [31mCONFIG_BFIN527_EZKIT_V2[0m || [31mCONFIG_BFIN532_IP0X[0m || [31mCONFIG_BLACKSTAMP[0m || [31mCONFIG_BFIN527_AD7160EVAL[0m)
default y
config [31mCONFIG_MEM_MT48H32M16LFCJ_75[0m
bool
depends on ([31mCONFIG_BFIN526_EZBRD[0m)
default y
config [31mCONFIG_MEM_MT47H64M16[0m
bool
depends on ([31mCONFIG_BFIN609_EZKIT[0m)
default y
source "arch/blackfin/mach-bf518/Kconfig"
source "arch/blackfin/mach-bf527/Kconfig"
source "arch/blackfin/mach-bf533/Kconfig"
source "arch/blackfin/mach-bf561/Kconfig"
source "arch/blackfin/mach-bf537/Kconfig"
source "arch/blackfin/mach-bf538/Kconfig"
source "arch/blackfin/mach-bf548/Kconfig"
source "arch/blackfin/mach-bf609/Kconfig"
menu "Board customizations"
config [31mCONFIG_CMDLINE_BOOL[0m
bool "Default bootloader kernel arguments"
config [31mCONFIG_CMDLINE[0m
string "Initial kernel command string"
depends on [31mCONFIG_CMDLINE_BOOL[0m
default "console=ttyBF0,57600"
help
If you don't have a boot loader capable of passing a command line string
to the kernel, you may specify one here. As a minimum, you should specify
the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
config [31mCONFIG_BOOT_LOAD[0m
hex "Kernel load address for booting"
default "0x1000"
range 0x1000 0x20000000
help
This option allows you to set the load address of the kernel.
This can be useful if you are on a board which has a small amount
of memory or you wish to reserve some memory at the beginning of
the address space.
Note that you need to keep this value above 4k (0x1000) as this
memory region is used to capture NULL pointer references as well
as some core kernel functions.
config [31mCONFIG_PHY_RAM_BASE_ADDRESS[0m
hex "Physical RAM Base"
default 0x0
help
set [31mCONFIG_BF609[0m [31mCONFIG_FPGA[0m physical [31mCONFIG_SRAM[0m base address
config [31mCONFIG_ROM_BASE[0m
hex "Kernel ROM Base"
depends on [31mCONFIG_ROMKERNEL[0m
default "0x20040040"
range 0x20000000 0x20400000 if !([31mCONFIG_BF54x[0m || [31mCONFIG_BF561[0m || [31mCONFIG_BF60x[0m)
range 0x20000000 0x30000000 if ([31mCONFIG_BF54x[0m || [31mCONFIG_BF561[0m)
range 0xB0000000 0xC0000000 if ([31mCONFIG_BF60x[0m)
help
Make sure your [31mCONFIG_ROM[0m base does not include any file-header
information that is prepended to the kernel.
For example, the bootable U-Boot format (created with
mkimage) has a 64 byte header (0x40). So while the image
you write to flash might start at say 0x20080000, you have
to add 0x40 to get the kernel's [31mCONFIG_ROM[0m base as it will come
after the header.
comment "Clock/PLL Setup"
config [31mCONFIG_CLKIN_HZ[0m
int "Frequency of the crystal on the board in Hz"
default "10000000" if [31mCONFIG_BFIN532_IP0X[0m
default "11059200" if [31mCONFIG_BFIN533_STAMP[0m
default "24576000" if [31mCONFIG_PNAV10[0m
default "25000000" # most people use this
default "27000000" if [31mCONFIG_BFIN533_EZKIT[0m
default "30000000" if [31mCONFIG_BFIN561_EZKIT[0m
default "24000000" if [31mCONFIG_BFIN527_AD7160EVAL[0m
help
The frequency of CLKIN crystal oscillator on the board in Hz.
Warning: This value should match the crystal on the board. Otherwise,
peripherals won't work properly.
config [31mCONFIG_BFIN_KERNEL_CLOCK[0m
bool "Re-program Clocks while Kernel boots?"
default n
help
This option decides if kernel clocks are re-programed from the
bootloader settings. If the clocks are not set, the SDRAM settings
are also not changed, and the Bootloader does 100% of the hardware
configuration.
config [31mCONFIG_PLL_BYPASS[0m
bool "Bypass PLL"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && (![31mCONFIG_BF60x[0m)
default n
config [31mCONFIG_CLKIN_HALF[0m
bool "Half Clock In"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && (! [31mCONFIG_PLL_BYPASS[0m)
default n
help
If this is set the clock will be divided by 2, before it goes to the PLL.
config [31mCONFIG_VCO_MULT[0m
int "VCO Multiplier"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && (! [31mCONFIG_PLL_BYPASS[0m)
range 1 64
default "22" if [31mCONFIG_BFIN533_EZKIT[0m
default "45" if [31mCONFIG_BFIN533_STAMP[0m
default "20" if ([31mCONFIG_BFIN537_STAMP[0m || [31mCONFIG_BFIN527_EZKIT[0m || [31mCONFIG_BFIN527_EZKIT_V2[0m || [31mCONFIG_BFIN548_EZKIT[0m || [31mCONFIG_BFIN548_BLUETECHNIX_CM[0m || [31mCONFIG_BFIN538_EZKIT[0m)
default "22" if [31mCONFIG_BFIN533_BLUETECHNIX_CM[0m
default "20" if ([31mCONFIG_BFIN537_BLUETECHNIX_CM_E[0m || [31mCONFIG_BFIN537_BLUETECHNIX_CM_U[0m || [31mCONFIG_BFIN527_BLUETECHNIX_CM[0m || [31mCONFIG_BFIN561_BLUETECHNIX_CM[0m)
default "20" if ([31mCONFIG_BFIN561_EZKIT[0m || [31mCONFIG_BF609[0m)
default "16" if ([31mCONFIG_H8606_HVSISTEMAS[0m || [31mCONFIG_BLACKSTAMP[0m || [31mCONFIG_BFIN526_EZBRD[0m || [31mCONFIG_BFIN518F_EZBRD[0m)
default "25" if [31mCONFIG_BFIN527_AD7160EVAL[0m
help
This controls the frequency of the on-chip PLL. This can be between 1 and 64.
PLL Frequency = (Crystal Frequency) * (this setting)
choice
prompt "Core Clock Divider"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m
default [31mCONFIG_CCLK_DIV_1[0m
help
This sets the frequency of the core. It can be 1, 2, 4 or 8
Core Frequency = (PLL frequency) / (this setting)
config [31mCONFIG_CCLK_DIV_1[0m
bool "1"
config [31mCONFIG_CCLK_DIV_2[0m
bool "2"
config [31mCONFIG_CCLK_DIV_4[0m
bool "4"
config [31mCONFIG_CCLK_DIV_8[0m
bool "8"
endchoice
config [31mCONFIG_SCLK_DIV[0m
int "System Clock Divider"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m
range 1 15
default 4
help
This sets the frequency of the system clock (including SDRAM or [31mCONFIG_DDR[0m) on
![31mCONFIG_BF60x[0m else it set the clock for system buses and provides the
source from which SCLK0 and SCLK1 are derived.
This can be between 1 and 15
System Clock = (PLL frequency) / (this setting)
config [31mCONFIG_SCLK0_DIV[0m
int "System Clock0 Divider"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && [31mCONFIG_BF60x[0m
range 1 15
default 1
help
This sets the frequency of the system clock0 for PVP and all other
peripherals not clocked by SCLK1.
This can be between 1 and 15
System Clock0 = (System Clock) / (this setting)
config [31mCONFIG_SCLK1_DIV[0m
int "System Clock1 Divider"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && [31mCONFIG_BF60x[0m
range 1 15
default 1
help
This sets the frequency of the system clock1 (including SPORT, [31mCONFIG_SPI[0m and ACM).
This can be between 1 and 15
System Clock1 = (System Clock) / (this setting)
config [31mCONFIG_DCLK_DIV[0m
int "DDR Clock Divider"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && [31mCONFIG_BF60x[0m
range 1 15
default 2
help
This sets the frequency of the [31mCONFIG_DDR[0m memory.
This can be between 1 and 15
[31mCONFIG_DDR[0m Clock = (PLL frequency) / (this setting)
choice
prompt "DDR SDRAM Chip Type"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m
depends on [31mCONFIG_BF54x[0m
default [31mCONFIG_MEM_MT46V32M16_5B[0m
config [31mCONFIG_MEM_MT46V32M16_6T[0m
bool "MT46V32M16_6T"
config [31mCONFIG_MEM_MT46V32M16_5B[0m
bool "MT46V32M16_5B"
endchoice
choice
prompt "DDR/SDRAM Timing"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK[0m && ![31mCONFIG_BF60x[0m
default [31mCONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC[0m
help
This option allows you to specify Blackfin SDRAM/[31mCONFIG_DDR[0m Timing parameters
The calculated SDRAM timing parameters may not be 100%
accurate - This option is therefore marked experimental.
config [31mCONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC[0m
bool "Calculate Timings"
config [31mCONFIG_BFIN_KERNEL_CLOCK_MEMINIT_SPEC[0m
bool "Provide accurate Timings based on target SCLK"
help
Please consult the Blackfin Hardware Reference Manuals as well
as the memory device datasheet.
http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
endchoice
menu "Memory Init Control"
depends on [31mCONFIG_BFIN_KERNEL_CLOCK_MEMINIT_SPEC[0m
config [31mCONFIG_MEM_DDRCTL0[0m
depends on [31mCONFIG_BF54x[0m
hex "DDRCTL0"
default 0x0
config [31mCONFIG_MEM_DDRCTL1[0m
depends on [31mCONFIG_BF54x[0m
hex "DDRCTL1"
default 0x0
config [31mCONFIG_MEM_DDRCTL2[0m
depends on [31mCONFIG_BF54x[0m
hex "DDRCTL2"
default 0x0
config [31mCONFIG_MEM_EBIU_DDRQUE[0m
depends on [31mCONFIG_BF54x[0m
hex "DDRQUE"
default 0x0
config [31mCONFIG_MEM_SDRRC[0m
depends on ![31mCONFIG_BF54x[0m
hex "SDRRC"
default 0x0
config [31mCONFIG_MEM_SDGCTL[0m
depends on ![31mCONFIG_BF54x[0m
hex "SDGCTL"
default 0x0
endmenu
#
# Max & Min Speeds for various Chips
#
config [31mCONFIG_MAX_VCO_HZ[0m
int
default 400000000 if [31mCONFIG_BF512[0m
default 400000000 if [31mCONFIG_BF514[0m
default 400000000 if [31mCONFIG_BF516[0m
default 400000000 if [31mCONFIG_BF518[0m
default 400000000 if [31mCONFIG_BF522[0m
default 600000000 if [31mCONFIG_BF523[0m
default 400000000 if [31mCONFIG_BF524[0m
default 600000000 if [31mCONFIG_BF525[0m
default 400000000 if [31mCONFIG_BF526[0m
default 600000000 if [31mCONFIG_BF527[0m
default 400000000 if [31mCONFIG_BF531[0m
default 400000000 if [31mCONFIG_BF532[0m
default 750000000 if [31mCONFIG_BF533[0m
default 500000000 if [31mCONFIG_BF534[0m
default 400000000 if [31mCONFIG_BF536[0m
default 600000000 if [31mCONFIG_BF537[0m
default 533333333 if [31mCONFIG_BF538[0m
default 533333333 if [31mCONFIG_BF539[0m
default 600000000 if [31mCONFIG_BF542[0m
default 533333333 if [31mCONFIG_BF544[0m
default 600000000 if [31mCONFIG_BF547[0m
default 600000000 if [31mCONFIG_BF548[0m
default 533333333 if [31mCONFIG_BF549[0m
default 600000000 if [31mCONFIG_BF561[0m
default 800000000 if [31mCONFIG_BF609[0m
config [31mCONFIG_MIN_VCO_HZ[0m
int
default 50000000
config [31mCONFIG_MAX_SCLK_HZ[0m
int
default 200000000 if [31mCONFIG_BF609[0m
default 133333333
config [31mCONFIG_MIN_SCLK_HZ[0m
int
default 27000000
comment "Kernel Timer/Scheduler"
source kernel/Kconfig.hz
config [31mCONFIG_SET_GENERIC_CLOCKEVENTS[0m
bool "Generic clock events"
default y
select [31mCONFIG_GENERIC_CLOCKEVENTS[0m
menu "Clock event device"
depends on [31mCONFIG_GENERIC_CLOCKEVENTS[0m
config [31mCONFIG_TICKSOURCE_GPTMR0[0m
bool "GPTimer0"
depends on ![31mCONFIG_SMP[0m
select [31mCONFIG_BFIN_GPTIMERS[0m
config [31mCONFIG_TICKSOURCE_CORETMR[0m
bool "Core timer"
default y
endmenu
menu "Clock source"
depends on [31mCONFIG_GENERIC_CLOCKEVENTS[0m
config [31mCONFIG_CYCLES_CLOCKSOURCE[0m
bool "CYCLES"
default y
depends on ![31mCONFIG_BFIN_SCRATCH_REG_CYCLES[0m
depends on ![31mCONFIG_SMP[0m
help
If you say Y here, you will enable support for using the 'cycles'
registers as a clock source. Doing so means you will be unable to
safely write to the 'cycles' register during runtime. You will
still be able to read it (such as for performance monitoring), but
writing the registers will most likely crash the kernel.
config [31mCONFIG_GPTMR0_CLOCKSOURCE[0m
bool "GPTimer0"
select [31mCONFIG_BFIN_GPTIMERS[0m
depends on ![31mCONFIG_TICKSOURCE_GPTMR0[0m
endmenu
comment "Misc"
choice
prompt "Blackfin Exception Scratch Register"
default [31mCONFIG_BFIN_SCRATCH_REG_RETN[0m
help
Select the resource to reserve for the Exception handler:
- RETN: Non-Maskable Interrupt (NMI)
- RETE: Exception Return (JTAG/[31mCONFIG_ICE[0m)
- CYCLES: Performance counter
If you are unsure, please select "RETN".
config [31mCONFIG_BFIN_SCRATCH_REG_RETN[0m
bool "RETN"
help
Use the RETN register in the Blackfin exception handler
as a stack scratch register. This means you cannot
safely use NMI on the Blackfin while running Linux, but
you can debug the system with a JTAG [31mCONFIG_ICE[0m and use the
CYCLES performance registers.
If you are unsure, please select "RETN".
config [31mCONFIG_BFIN_SCRATCH_REG_RETE[0m
bool "RETE"
help
Use the RETE register in the Blackfin exception handler
as a stack scratch register. This means you cannot
safely use a JTAG [31mCONFIG_ICE[0m while debugging a Blackfin board,
but you can safely use the CYCLES performance registers
and the NMI.
If you are unsure, please select "RETN".
config [31mCONFIG_BFIN_SCRATCH_REG_CYCLES[0m
bool "CYCLES"
help
Use the CYCLES register in the Blackfin exception handler
as a stack scratch register. This means you cannot
safely use the CYCLES performance registers on a Blackfin
board at anytime, but you can debug the system with a JTAG
[31mCONFIG_ICE[0m and use the NMI.
If you are unsure, please select "RETN".
endchoice
endmenu
menu "Blackfin Kernel Optimizations"
comment "Memory Optimizations"
config [31mCONFIG_I_ENTRY_L1[0m
bool "Locate interrupt entry code in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_EXCPT_IRQ_SYSC_L1[0m
bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the entire ASM lowlevel exception and interrupt entry code
(STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency)
config [31mCONFIG_DO_IRQ_L1[0m
bool "Locate frequently called do_irq dispatcher function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the frequently called do_irq dispatcher function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_CORE_TIMER_IRQ_L1[0m
bool "Locate frequently called timer_interrupt() function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the frequently called timer_interrupt() function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_IDLE_L1[0m
bool "Locate frequently idle function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the frequently called idle function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_SCHEDULE_L1[0m
bool "Locate kernel schedule function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the frequently called kernel schedule is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_ARITHMETIC_OPS_L1[0m
bool "Locate kernel owned arithmetic functions in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, arithmetic functions are linked
into L1 instruction memory. (less latency)
config [31mCONFIG_ACCESS_OK_L1[0m
bool "Locate access_ok function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the access_ok function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_MEMSET_L1[0m
bool "Locate memset function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the memset function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_MEMCPY_L1[0m
bool "Locate memcpy function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the memcpy function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_STRCMP_L1[0m
bool "locate strcmp function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the strcmp function is linked
into L1 instruction memory (less latency).
config [31mCONFIG_STRNCMP_L1[0m
bool "locate strncmp function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the strncmp function is linked
into L1 instruction memory (less latency).
config [31mCONFIG_STRCPY_L1[0m
bool "locate strcpy function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the strcpy function is linked
into L1 instruction memory (less latency).
config [31mCONFIG_STRNCPY_L1[0m
bool "locate strncpy function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the strncpy function is linked
into L1 instruction memory (less latency).
config [31mCONFIG_SYS_BFIN_SPINLOCK_L1[0m
bool "Locate sys_bfin_spinlock function in L1 Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, sys_bfin_spinlock function is linked
into L1 instruction memory. (less latency)
config [31mCONFIG_CACHELINE_ALIGNED_L1[0m
bool "Locate cacheline_aligned data to L1 Data Memory"
default y if ![31mCONFIG_BF54x[0m
default n if [31mCONFIG_BF54x[0m
depends on ![31mCONFIG_SMP[0m && ![31mCONFIG_BF531[0m && ![31mCONFIG_CRC32[0m
help
If enabled, cacheline_aligned data is linked
into L1 data memory. (less latency)
config [31mCONFIG_SYSCALL_TAB_L1[0m
bool "Locate Syscall Table L1 Data Memory"
default n
depends on ![31mCONFIG_SMP[0m && ![31mCONFIG_BF531[0m
help
If enabled, the Syscall LUT is linked
into L1 data memory. (less latency)
config [31mCONFIG_CPLB_SWITCH_TAB_L1[0m
bool "Locate CPLB Switch Tables L1 Data Memory"
default n
depends on ![31mCONFIG_SMP[0m && ![31mCONFIG_BF531[0m
help
If enabled, the CPLB Switch Tables are linked
into L1 data memory. (less latency)
config [31mCONFIG_ICACHE_FLUSH_L1[0m
bool "Locate icache flush funcs in L1 Inst Memory"
default y
help
If enabled, the Blackfin icache flushing functions are linked
into L1 instruction memory.
Note that this might be required to address anomalies, but
these functions are pretty small, so it shouldn't be too bad.
If you are using a processor affected by an anomaly, the build
system will double check for you and prevent it.
config [31mCONFIG_DCACHE_FLUSH_L1[0m
bool "Locate dcache flush funcs in L1 Inst Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled, the Blackfin dcache flushing functions are linked
into L1 instruction memory.
config [31mCONFIG_APP_STACK_L1[0m
bool "Support locating application stack in L1 Scratch Memory"
default y
depends on ![31mCONFIG_SMP[0m
help
If enabled the application stack can be located in L1
scratch memory (less latency).
Currently only works with FLAT binaries.
config [31mCONFIG_EXCEPTION_L1_SCRATCH[0m
bool "Locate exception stack in L1 Scratch Memory"
default n
depends on ![31mCONFIG_SMP[0m && ![31mCONFIG_APP_STACK_L1[0m
help
Whenever an exception occurs, use the L1 Scratch memory for
stack storage. You cannot place the stacks of FLAT binaries
in L1 when using this option.
If you don't use L1 Scratch, then you should say Y here.
comment "Speed Optimizations"
config [31mCONFIG_BFIN_INS_LOWOVERHEAD[0m
bool "ins[bwl] low overhead, higher interrupt latency"
default y
depends on ![31mCONFIG_SMP[0m
help
Reads on the Blackfin are speculative. In Blackfin terms, this means
they can be interrupted at any time (even after they have been issued
on to the external bus), and re-issued after the interrupt occurs.
For memory - this is not a big deal, since memory does not change if
it sees a read.
If a FIFO is sitting on the end of the read, it will see two reads,
when the core only sees one since the FIFO receives both the read
which is cancelled (and not delivered to the core) and the one which
is re-issued (which is delivered to the core).
To solve this, interrupts are turned off before reads occur to
I/O space. This option controls which the overhead/latency of
controlling interrupts during this time
"n" turns interrupts off every read
(higher overhead, but lower interrupt latency)
"y" turns interrupts off every loop
(low overhead, but longer interrupt latency)
default behavior is to leave this set to on (type "Y"). If you are experiencing
interrupt latency issues, it is safe and OK to turn this off.
endmenu
choice
prompt "Kernel executes from"
help
Choose the memory type that the kernel will be running in.
config [31mCONFIG_RAMKERNEL[0m
bool "RAM"
help
The kernel will be resident in RAM when running.
config [31mCONFIG_ROMKERNEL[0m
bool "ROM"
help
The kernel will be resident in FLASH/[31mCONFIG_ROM[0m when running.
endchoice
# Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
config [31mCONFIG_XIP_KERNEL[0m
bool
default y
depends on [31mCONFIG_ROMKERNEL[0m
source "mm/Kconfig"
config [31mCONFIG_BFIN_GPTIMERS[0m
tristate "Enable Blackfin General Purpose Timers API"
default n
help
Enable support for the General Purpose Timers API. If you
are unsure, say N.
To compile this driver as a module, choose [31mCONFIG_M[0m here: the module
will be called gptimers.
choice
prompt "Uncached DMA region"
default [31mCONFIG_DMA_UNCACHED_1M[0m
config [31mCONFIG_DMA_UNCACHED_32M[0m
bool "Enable 32M DMA region"
config [31mCONFIG_DMA_UNCACHED_16M[0m
bool "Enable 16M DMA region"
config [31mCONFIG_DMA_UNCACHED_8M[0m
bool "Enable 8M DMA region"
config [31mCONFIG_DMA_UNCACHED_4M[0m
bool "Enable 4M DMA region"
config [31mCONFIG_DMA_UNCACHED_2M[0m
bool "Enable 2M DMA region"
config [31mCONFIG_DMA_UNCACHED_1M[0m
bool "Enable 1M DMA region"
config [31mCONFIG_DMA_UNCACHED_512K[0m
bool "Enable 512K DMA region"
config [31mCONFIG_DMA_UNCACHED_256K[0m
bool "Enable 256K DMA region"
config [31mCONFIG_DMA_UNCACHED_128K[0m
bool "Enable 128K DMA region"
config [31mCONFIG_DMA_UNCACHED_NONE[0m
bool "Disable DMA region"
endchoice
comment "Cache Support"
config [31mCONFIG_BFIN_ICACHE[0m
bool "Enable ICACHE"
default y
config [31mCONFIG_BFIN_EXTMEM_ICACHEABLE[0m
bool "Enable ICACHE for external memory"
depends on [31mCONFIG_BFIN_ICACHE[0m
default y
config [31mCONFIG_BFIN_L2_ICACHEABLE[0m
bool "Enable ICACHE for L2 SRAM"
depends on [31mCONFIG_BFIN_ICACHE[0m
depends on ([31mCONFIG_BF54x[0m || [31mCONFIG_BF561[0m || [31mCONFIG_BF60x[0m) && ![31mCONFIG_SMP[0m
default n
config [31mCONFIG_BFIN_DCACHE[0m
bool "Enable DCACHE"
default y
config [31mCONFIG_BFIN_DCACHE_BANKA[0m
bool "Enable only 16k BankA DCACHE - BankB is SRAM"
depends on [31mCONFIG_BFIN_DCACHE[0m && ![31mCONFIG_BF531[0m
default n
config [31mCONFIG_BFIN_EXTMEM_DCACHEABLE[0m
bool "Enable DCACHE for external memory"
depends on [31mCONFIG_BFIN_DCACHE[0m
default y
choice
prompt "External memory DCACHE policy"
depends on [31mCONFIG_BFIN_EXTMEM_DCACHEABLE[0m
default [31mCONFIG_BFIN_EXTMEM_WRITEBACK[0m if ![31mCONFIG_SMP[0m
default [31mCONFIG_BFIN_EXTMEM_WRITETHROUGH[0m if [31mCONFIG_SMP[0m
config [31mCONFIG_BFIN_EXTMEM_WRITEBACK[0m
bool "Write back"
depends on ![31mCONFIG_SMP[0m
help
Write Back Policy:
Cached data will be written back to SDRAM only when needed.
This can give a nice increase in performance, but beware of
broken drivers that do not properly invalidate/flush their
cache.
Write Through Policy:
Cached data will always be written back to SDRAM when the
cache is updated. This is a completely safe setting, but
performance is worse than Write Back.
If you are unsure of the options and you want to be safe,
then go with Write Through.
config [31mCONFIG_BFIN_EXTMEM_WRITETHROUGH[0m
bool "Write through"
help
Write Back Policy:
Cached data will be written back to SDRAM only when needed.
This can give a nice increase in performance, but beware of
broken drivers that do not properly invalidate/flush their
cache.
Write Through Policy:
Cached data will always be written back to SDRAM when the
cache is updated. This is a completely safe setting, but
performance is worse than Write Back.
If you are unsure of the options and you want to be safe,
then go with Write Through.
endchoice
config [31mCONFIG_BFIN_L2_DCACHEABLE[0m
bool "Enable DCACHE for L2 SRAM"
depends on [31mCONFIG_BFIN_DCACHE[0m
depends on ([31mCONFIG_BF54x[0m || [31mCONFIG_BF561[0m || [31mCONFIG_BF60x[0m) && ![31mCONFIG_SMP[0m
default n
choice
prompt "L2 SRAM DCACHE policy"
depends on [31mCONFIG_BFIN_L2_DCACHEABLE[0m
default [31mCONFIG_BFIN_L2_WRITEBACK[0m
config [31mCONFIG_BFIN_L2_WRITEBACK[0m
bool "Write back"
config [31mCONFIG_BFIN_L2_WRITETHROUGH[0m
bool "Write through"
endchoice
comment "Memory Protection Unit"
config [31mCONFIG_MPU[0m
bool "Enable the memory protection unit"
default n
help
Use the processor's [31mCONFIG_MPU[0m to protect applications from accessing
memory they do not own. This comes at a performance penalty
and is recommended only for debugging.
comment "Asynchronous Memory Configuration"
menu "EBIU_AMGCTL Global Control"
depends on ![31mCONFIG_BF60x[0m
config [31mCONFIG_C_AMCKEN[0m
bool "Enable CLKOUT"
default y
config [31mCONFIG_C_CDPRIO[0m
bool "DMA has priority over core for ext. accesses"
default n
config [31mCONFIG_C_B0PEN[0m
depends on [31mCONFIG_BF561[0m
bool "Bank 0 16 bit packing enable"
default y
config [31mCONFIG_C_B1PEN[0m
depends on [31mCONFIG_BF561[0m
bool "Bank 1 16 bit packing enable"
default y
config [31mCONFIG_C_B2PEN[0m
depends on [31mCONFIG_BF561[0m
bool "Bank 2 16 bit packing enable"
default y
config [31mCONFIG_C_B3PEN[0m
depends on [31mCONFIG_BF561[0m
bool "Bank 3 16 bit packing enable"
default n
choice
prompt "Enable Asynchronous Memory Banks"
default [31mCONFIG_C_AMBEN_ALL[0m
config [31mCONFIG_C_AMBEN[0m
bool "Disable All Banks"
config [31mCONFIG_C_AMBEN_B0[0m
bool "Enable Bank 0"
config [31mCONFIG_C_AMBEN_B0_B1[0m
bool "Enable Bank 0 & 1"
config [31mCONFIG_C_AMBEN_B0_B1_B2[0m
bool "Enable Bank 0 & 1 & 2"
config [31mCONFIG_C_AMBEN_ALL[0m
bool "Enable All Banks"
endchoice
endmenu
menu "EBIU_AMBCTL Control"
depends on ![31mCONFIG_BF60x[0m
config [31mCONFIG_BANK_0[0m
hex "Bank 0 (AMBCTL0.L)"
default 0x7BB0
help
These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
used to control the Asynchronous Memory Bank 0 settings.
config [31mCONFIG_BANK_1[0m
hex "Bank 1 (AMBCTL0.H)"
default 0x7BB0
default 0x5558 if [31mCONFIG_BF54x[0m
help
These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
used to control the Asynchronous Memory Bank 1 settings.
config [31mCONFIG_BANK_2[0m
hex "Bank 2 (AMBCTL1.L)"
default 0x7BB0
help
These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
used to control the Asynchronous Memory Bank 2 settings.
config [31mCONFIG_BANK_3[0m
hex "Bank 3 (AMBCTL1.H)"
default 0x99B3
help
These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
used to control the Asynchronous Memory Bank 3 settings.
endmenu
config [31mCONFIG_EBIU_MBSCTLVAL[0m
hex "EBIU Bank Select Control Register"
depends on [31mCONFIG_BF54x[0m
default 0
config [31mCONFIG_EBIU_MODEVAL[0m
hex "Flash Memory Mode Control Register"
depends on [31mCONFIG_BF54x[0m
default 1
config [31mCONFIG_EBIU_FCTLVAL[0m
hex "Flash Memory Bank Control Register"
depends on [31mCONFIG_BF54x[0m
default 6
endmenu
#############################################################################
menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
config [31mCONFIG_PCI[0m
bool "PCI support"
depends on [31mCONFIG_BROKEN[0m
help
Support for [31mCONFIG_PCI[0m bus.
source "drivers/pci/Kconfig"
source "drivers/pcmcia/Kconfig"
endmenu
menu "Executable file formats"
source "fs/Kconfig.binfmt"
endmenu
menu "Power management options"
source "kernel/power/Kconfig"
config [31mCONFIG_ARCH_SUSPEND_POSSIBLE[0m
def_bool y
choice
prompt "Standby Power Saving Mode"
depends on [31mCONFIG_PM[0m && ![31mCONFIG_BF60x[0m
default [31mCONFIG_PM_BFIN_SLEEP_DEEPER[0m
config [31mCONFIG_PM_BFIN_SLEEP_DEEPER[0m
bool "Sleep Deeper"
help
Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
power dissipation by disabling the clock to the processor core (CCLK).
Furthermore, Standby sets the internal power supply voltage (VDDINT)
to 0.85 V to provide the greatest power savings, while preserving the
processor state.
The PLL and system clock (SCLK) continue to operate at a very low
frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
the SDRAM is put into Self Refresh Mode. Typically an external event
such as GPIO interrupt or [31mCONFIG_RTC[0m activity wakes up the processor.
Various Peripherals such as UART, SPORT, PPI may not function as
normal during Sleep Deeper, due to the reduced SCLK frequency.
When in the sleep mode, system DMA access to L1 memory is not supported.
If unsure, select "Sleep Deeper".
config [31mCONFIG_PM_BFIN_SLEEP[0m
bool "Sleep"
help
Sleep Mode (High Power Savings) - The sleep mode reduces power
dissipation by disabling the clock to the processor core (CCLK).
The PLL and system clock (SCLK), however, continue to operate in
this mode. Typically an external event or [31mCONFIG_RTC[0m activity will wake
up the processor. When in the sleep mode, system DMA access to L1
memory is not supported.
If unsure, select "Sleep Deeper".
endchoice
comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
depends on [31mCONFIG_PM[0m
config [31mCONFIG_PM_BFIN_WAKE_PH6[0m
bool "Allow Wake-Up from on-chip PHY or PH6 GP"
depends on [31mCONFIG_PM[0m && ([31mCONFIG_BF51x[0m || [31mCONFIG_BF52x[0m || [31mCONFIG_BF534[0m || [31mCONFIG_BF536[0m || [31mCONFIG_BF537[0m)
default n
help
Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
config [31mCONFIG_PM_BFIN_WAKE_GP[0m
bool "Allow Wake-Up from GPIOs"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF54x[0m
default n
help
Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
(all processors, except ADSP-[31mCONFIG_BF549[0m). This option sets
the general-purpose wake-up enable (GPWE) control bit to enable
wake-up upon detection of an active low signal on the /GPW (PH7) pin.
On ADSP-[31mCONFIG_BF549[0m this option enables the same functionality on the
/MRXON pin also PH7.
config [31mCONFIG_PM_BFIN_WAKE_PA15[0m
bool "Allow Wake-Up from PA15"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PA15 Wake-Up
config [31mCONFIG_PM_BFIN_WAKE_PA15_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PA15[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PB15[0m
bool "Allow Wake-Up from PB15"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PB15 Wake-Up
config [31mCONFIG_PM_BFIN_WAKE_PB15_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PB15[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PC15[0m
bool "Allow Wake-Up from PC15"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PC15 Wake-Up
config [31mCONFIG_PM_BFIN_WAKE_PC15_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PC15[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PD06[0m
bool "Allow Wake-Up from PD06(ETH0_PHYINT)"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PD06(ETH0_PHYINT) Wake-up
config [31mCONFIG_PM_BFIN_WAKE_PD06_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PD06[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PE12[0m
bool "Allow Wake-Up from PE12(ETH1_PHYINT, PUSH BUTTON)"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PE12(ETH1_PHYINT, PUSH BUTTON) Wake-up
config [31mCONFIG_PM_BFIN_WAKE_PE12_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PE12[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PG04[0m
bool "Allow Wake-Up from PG04(CAN0_RX)"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PG04(CAN0_RX) Wake-up
config [31mCONFIG_PM_BFIN_WAKE_PG04_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PG04[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_PG13[0m
bool "Allow Wake-Up from PG13"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable PG13 Wake-Up
config [31mCONFIG_PM_BFIN_WAKE_PG13_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_PG13[0m
default 0
help
Wake-Up priority 0(low) 1(high)
config [31mCONFIG_PM_BFIN_WAKE_USB[0m
bool "Allow Wake-Up from (USB)"
depends on [31mCONFIG_PM[0m && [31mCONFIG_BF60x[0m
default n
help
Enable ([31mCONFIG_USB[0m) Wake-up
config [31mCONFIG_PM_BFIN_WAKE_USB_POL[0m
int "Wake-up priority"
depends on [31mCONFIG_PM_BFIN_WAKE_USB[0m
default 0
help
Wake-Up priority 0(low) 1(high)
endmenu
menu "CPU Frequency scaling"
source "drivers/cpufreq/Kconfig"
config [31mCONFIG_BFIN_CPU_FREQ[0m
bool
depends on [31mCONFIG_CPU_FREQ[0m
default y
config [31mCONFIG_CPU_VOLTAGE[0m
bool "CPU Voltage scaling"
depends on [31mCONFIG_CPU_FREQ[0m
default n
help
Say Y here if you want CPU voltage scaling according to the CPU frequency.
This option violates the PLL BYPASS recommendation in the Blackfin Processor
manuals. There is a theoretical risk that during VDDINT transitions
the PLL may unlock.
endmenu
source "net/Kconfig"
source "drivers/Kconfig"
source "drivers/firmware/Kconfig"
source "fs/Kconfig"
source "arch/blackfin/Kconfig.debug"
source "security/Kconfig"
source "crypto/Kconfig"
source "lib/Kconfig"