Training courses

Kernel and Embedded Linux

Bootlin training courses

Embedded Linux, kernel,
Yocto Project, Buildroot, real-time,
graphics, boot time, debugging...

Bootlin logo

Elixir Cross Referencer

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
#ifndef __gio_defs_h
#define __gio_defs_h

/*
 * This file is autogenerated from
 *   file:           gio.r
 * 
 *   by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
 * Any changes here will be lost.
 *
 * -*- buffer-read-only: t -*-
 */
/* Main access macros */
#ifndef REG_RD
#define REG_RD( scope, inst, reg ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR
#define REG_WR( scope, inst, reg, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_VECT
#define REG_RD_VECT( scope, inst, reg, index ) \
  REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_VECT
#define REG_WR_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT
#define REG_RD_INT( scope, inst, reg ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_WR_INT
#define REG_WR_INT( scope, inst, reg, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#endif

#ifndef REG_RD_INT_VECT
#define REG_RD_INT_VECT( scope, inst, reg, index ) \
  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
	    (index) * STRIDE_##scope##_##reg )
#endif

#ifndef REG_WR_INT_VECT
#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
	     (index) * STRIDE_##scope##_##reg, (val) )
#endif

#ifndef REG_TYPE_CONV
#define REG_TYPE_CONV( type, orgtype, val ) \
  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#endif

#ifndef reg_page_size
#define reg_page_size 8192
#endif

#ifndef REG_ADDR
#define REG_ADDR( scope, inst, reg ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg )
#endif

#ifndef REG_ADDR_VECT
#define REG_ADDR_VECT( scope, inst, reg, index ) \
  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )
#endif

/* C-code for register scope gio */

/* Register r_pa_din, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pa_din;
#define REG_RD_ADDR_gio_r_pa_din 0

/* Register rw_pa_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 32;
} reg_gio_rw_pa_dout;
#define REG_RD_ADDR_gio_rw_pa_dout 4
#define REG_WR_ADDR_gio_rw_pa_dout 4

/* Register rw_pa_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 32;
} reg_gio_rw_pa_oe;
#define REG_RD_ADDR_gio_rw_pa_oe 8
#define REG_WR_ADDR_gio_rw_pa_oe 8

/* Register rw_pa_byte0_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte0_dout;
#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12

/* Register rw_pa_byte0_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte0_oe;
#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16

/* Register rw_pa_byte1_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte1_dout;
#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20

/* Register rw_pa_byte1_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte1_oe;
#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24

/* Register rw_pa_byte2_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte2_dout;
#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28

/* Register rw_pa_byte2_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte2_oe;
#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32

/* Register rw_pa_byte3_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte3_dout;
#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36

/* Register rw_pa_byte3_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pa_byte3_oe;
#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40

/* Register r_pb_din, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pb_din;
#define REG_RD_ADDR_gio_r_pb_din 44

/* Register rw_pb_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 32;
} reg_gio_rw_pb_dout;
#define REG_RD_ADDR_gio_rw_pb_dout 48
#define REG_WR_ADDR_gio_rw_pb_dout 48

/* Register rw_pb_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 32;
} reg_gio_rw_pb_oe;
#define REG_RD_ADDR_gio_rw_pb_oe 52
#define REG_WR_ADDR_gio_rw_pb_oe 52

/* Register rw_pb_byte0_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte0_dout;
#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56

/* Register rw_pb_byte0_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte0_oe;
#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60

/* Register rw_pb_byte1_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte1_dout;
#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64

/* Register rw_pb_byte1_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte1_oe;
#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68

/* Register rw_pb_byte2_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte2_dout;
#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72

/* Register rw_pb_byte2_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte2_oe;
#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76

/* Register rw_pb_byte3_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte3_dout;
#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80

/* Register rw_pb_byte3_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pb_byte3_oe;
#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84

/* Register r_pc_din, scope gio, type r */
typedef struct {
  unsigned int data : 16;
  unsigned int dummy1 : 16;
} reg_gio_r_pc_din;
#define REG_RD_ADDR_gio_r_pc_din 88

/* Register rw_pc_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 16;
  unsigned int dummy1 : 16;
} reg_gio_rw_pc_dout;
#define REG_RD_ADDR_gio_rw_pc_dout 92
#define REG_WR_ADDR_gio_rw_pc_dout 92

/* Register rw_pc_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 16;
  unsigned int dummy1 : 16;
} reg_gio_rw_pc_oe;
#define REG_RD_ADDR_gio_rw_pc_oe 96
#define REG_WR_ADDR_gio_rw_pc_oe 96

/* Register rw_pc_byte0_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte0_dout;
#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100

/* Register rw_pc_byte0_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte0_oe;
#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104

/* Register rw_pc_byte1_dout, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte1_dout;
#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108

/* Register rw_pc_byte1_oe, scope gio, type rw */
typedef struct {
  unsigned int oe : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pc_byte1_oe;
#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112

/* Register r_pd_din, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pd_din;
#define REG_RD_ADDR_gio_r_pd_din 116

/* Register rw_intr_cfg, scope gio, type rw */
typedef struct {
  unsigned int intr0 : 3;
  unsigned int intr1 : 3;
  unsigned int intr2 : 3;
  unsigned int intr3 : 3;
  unsigned int intr4 : 3;
  unsigned int intr5 : 3;
  unsigned int intr6 : 3;
  unsigned int intr7 : 3;
  unsigned int dummy1 : 8;
} reg_gio_rw_intr_cfg;
#define REG_RD_ADDR_gio_rw_intr_cfg 120
#define REG_WR_ADDR_gio_rw_intr_cfg 120

/* Register rw_intr_pins, scope gio, type rw */
typedef struct {
  unsigned int intr0 : 4;
  unsigned int intr1 : 4;
  unsigned int intr2 : 4;
  unsigned int intr3 : 4;
  unsigned int intr4 : 4;
  unsigned int intr5 : 4;
  unsigned int intr6 : 4;
  unsigned int intr7 : 4;
} reg_gio_rw_intr_pins;
#define REG_RD_ADDR_gio_rw_intr_pins 124
#define REG_WR_ADDR_gio_rw_intr_pins 124

/* Register rw_intr_mask, scope gio, type rw */
typedef struct {
  unsigned int intr0     : 1;
  unsigned int intr1     : 1;
  unsigned int intr2     : 1;
  unsigned int intr3     : 1;
  unsigned int intr4     : 1;
  unsigned int intr5     : 1;
  unsigned int intr6     : 1;
  unsigned int intr7     : 1;
  unsigned int i2c0_done : 1;
  unsigned int i2c1_done : 1;
  unsigned int dummy1    : 22;
} reg_gio_rw_intr_mask;
#define REG_RD_ADDR_gio_rw_intr_mask 128
#define REG_WR_ADDR_gio_rw_intr_mask 128

/* Register rw_ack_intr, scope gio, type rw */
typedef struct {
  unsigned int intr0     : 1;
  unsigned int intr1     : 1;
  unsigned int intr2     : 1;
  unsigned int intr3     : 1;
  unsigned int intr4     : 1;
  unsigned int intr5     : 1;
  unsigned int intr6     : 1;
  unsigned int intr7     : 1;
  unsigned int i2c0_done : 1;
  unsigned int i2c1_done : 1;
  unsigned int dummy1    : 22;
} reg_gio_rw_ack_intr;
#define REG_RD_ADDR_gio_rw_ack_intr 132
#define REG_WR_ADDR_gio_rw_ack_intr 132

/* Register r_intr, scope gio, type r */
typedef struct {
  unsigned int intr0     : 1;
  unsigned int intr1     : 1;
  unsigned int intr2     : 1;
  unsigned int intr3     : 1;
  unsigned int intr4     : 1;
  unsigned int intr5     : 1;
  unsigned int intr6     : 1;
  unsigned int intr7     : 1;
  unsigned int i2c0_done : 1;
  unsigned int i2c1_done : 1;
  unsigned int dummy1    : 22;
} reg_gio_r_intr;
#define REG_RD_ADDR_gio_r_intr 136

/* Register r_masked_intr, scope gio, type r */
typedef struct {
  unsigned int intr0     : 1;
  unsigned int intr1     : 1;
  unsigned int intr2     : 1;
  unsigned int intr3     : 1;
  unsigned int intr4     : 1;
  unsigned int intr5     : 1;
  unsigned int intr6     : 1;
  unsigned int intr7     : 1;
  unsigned int i2c0_done : 1;
  unsigned int i2c1_done : 1;
  unsigned int dummy1    : 22;
} reg_gio_r_masked_intr;
#define REG_RD_ADDR_gio_r_masked_intr 140

/* Register rw_i2c0_start, scope gio, type rw */
typedef struct {
  unsigned int run : 1;
  unsigned int dummy1 : 31;
} reg_gio_rw_i2c0_start;
#define REG_RD_ADDR_gio_rw_i2c0_start 144
#define REG_WR_ADDR_gio_rw_i2c0_start 144

/* Register rw_i2c0_cfg, scope gio, type rw */
typedef struct {
  unsigned int en        : 1;
  unsigned int bit_order : 1;
  unsigned int scl_io    : 1;
  unsigned int scl_inv   : 1;
  unsigned int sda_io    : 1;
  unsigned int sda_idle  : 1;
  unsigned int dummy1    : 26;
} reg_gio_rw_i2c0_cfg;
#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
#define REG_WR_ADDR_gio_rw_i2c0_cfg 148

/* Register rw_i2c0_ctrl, scope gio, type rw */
typedef struct {
  unsigned int trf_bits    : 6;
  unsigned int switch_dir  : 6;
  unsigned int extra_start : 3;
  unsigned int early_end   : 1;
  unsigned int start_stop  : 1;
  unsigned int ack_dir0    : 1;
  unsigned int ack_dir1    : 1;
  unsigned int ack_dir2    : 1;
  unsigned int ack_dir3    : 1;
  unsigned int ack_dir4    : 1;
  unsigned int ack_dir5    : 1;
  unsigned int ack_bit     : 1;
  unsigned int start_bit   : 1;
  unsigned int freq        : 2;
  unsigned int dummy1      : 5;
} reg_gio_rw_i2c0_ctrl;
#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152

/* Register rw_i2c0_data, scope gio, type rw */
typedef struct {
  unsigned int data0 : 8;
  unsigned int data1 : 8;
  unsigned int data2 : 8;
  unsigned int data3 : 8;
} reg_gio_rw_i2c0_data;
#define REG_RD_ADDR_gio_rw_i2c0_data 156
#define REG_WR_ADDR_gio_rw_i2c0_data 156

/* Register rw_i2c0_data2, scope gio, type rw */
typedef struct {
  unsigned int data4     : 8;
  unsigned int data5     : 8;
  unsigned int start_val : 6;
  unsigned int ack_val   : 6;
  unsigned int dummy1    : 4;
} reg_gio_rw_i2c0_data2;
#define REG_RD_ADDR_gio_rw_i2c0_data2 160
#define REG_WR_ADDR_gio_rw_i2c0_data2 160

/* Register rw_i2c1_start, scope gio, type rw */
typedef struct {
  unsigned int run : 1;
  unsigned int dummy1 : 31;
} reg_gio_rw_i2c1_start;
#define REG_RD_ADDR_gio_rw_i2c1_start 164
#define REG_WR_ADDR_gio_rw_i2c1_start 164

/* Register rw_i2c1_cfg, scope gio, type rw */
typedef struct {
  unsigned int en        : 1;
  unsigned int bit_order : 1;
  unsigned int scl_io    : 1;
  unsigned int scl_inv   : 1;
  unsigned int sda0_io   : 1;
  unsigned int sda0_idle : 1;
  unsigned int sda1_io   : 1;
  unsigned int sda1_idle : 1;
  unsigned int sda2_io   : 1;
  unsigned int sda2_idle : 1;
  unsigned int sda3_io   : 1;
  unsigned int sda3_idle : 1;
  unsigned int sda_sel   : 2;
  unsigned int sen_idle  : 1;
  unsigned int sen_inv   : 1;
  unsigned int sen_sel   : 2;
  unsigned int dummy1    : 14;
} reg_gio_rw_i2c1_cfg;
#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
#define REG_WR_ADDR_gio_rw_i2c1_cfg 168

/* Register rw_i2c1_ctrl, scope gio, type rw */
typedef struct {
  unsigned int trf_bits    : 6;
  unsigned int switch_dir  : 6;
  unsigned int extra_start : 3;
  unsigned int early_end   : 1;
  unsigned int start_stop  : 1;
  unsigned int ack_dir0    : 1;
  unsigned int ack_dir1    : 1;
  unsigned int ack_dir2    : 1;
  unsigned int ack_dir3    : 1;
  unsigned int ack_dir4    : 1;
  unsigned int ack_dir5    : 1;
  unsigned int ack_bit     : 1;
  unsigned int start_bit   : 1;
  unsigned int freq        : 2;
  unsigned int dummy1      : 5;
} reg_gio_rw_i2c1_ctrl;
#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172

/* Register rw_i2c1_data, scope gio, type rw */
typedef struct {
  unsigned int data0 : 8;
  unsigned int data1 : 8;
  unsigned int data2 : 8;
  unsigned int data3 : 8;
} reg_gio_rw_i2c1_data;
#define REG_RD_ADDR_gio_rw_i2c1_data 176
#define REG_WR_ADDR_gio_rw_i2c1_data 176

/* Register rw_i2c1_data2, scope gio, type rw */
typedef struct {
  unsigned int data4     : 8;
  unsigned int data5     : 8;
  unsigned int start_val : 6;
  unsigned int ack_val   : 6;
  unsigned int dummy1    : 4;
} reg_gio_rw_i2c1_data2;
#define REG_RD_ADDR_gio_rw_i2c1_data2 180
#define REG_WR_ADDR_gio_rw_i2c1_data2 180

/* Register r_ppwm_stat, scope gio, type r */
typedef struct {
  unsigned int freq : 2;
  unsigned int dummy1 : 30;
} reg_gio_r_ppwm_stat;
#define REG_RD_ADDR_gio_r_ppwm_stat 184

/* Register rw_ppwm_data, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_ppwm_data;
#define REG_RD_ADDR_gio_rw_ppwm_data 188
#define REG_WR_ADDR_gio_rw_ppwm_data 188

/* Register rw_pwm0_ctrl, scope gio, type rw */
typedef struct {
  unsigned int mode         : 2;
  unsigned int ccd_override : 1;
  unsigned int ccd_val      : 1;
  unsigned int dummy1       : 28;
} reg_gio_rw_pwm0_ctrl;
#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192

/* Register rw_pwm0_var, scope gio, type rw */
typedef struct {
  unsigned int lo : 13;
  unsigned int hi : 13;
  unsigned int dummy1 : 6;
} reg_gio_rw_pwm0_var;
#define REG_RD_ADDR_gio_rw_pwm0_var 196
#define REG_WR_ADDR_gio_rw_pwm0_var 196

/* Register rw_pwm0_data, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pwm0_data;
#define REG_RD_ADDR_gio_rw_pwm0_data 200
#define REG_WR_ADDR_gio_rw_pwm0_data 200

/* Register rw_pwm1_ctrl, scope gio, type rw */
typedef struct {
  unsigned int mode         : 2;
  unsigned int ccd_override : 1;
  unsigned int ccd_val      : 1;
  unsigned int dummy1       : 28;
} reg_gio_rw_pwm1_ctrl;
#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204

/* Register rw_pwm1_var, scope gio, type rw */
typedef struct {
  unsigned int lo : 13;
  unsigned int hi : 13;
  unsigned int dummy1 : 6;
} reg_gio_rw_pwm1_var;
#define REG_RD_ADDR_gio_rw_pwm1_var 208
#define REG_WR_ADDR_gio_rw_pwm1_var 208

/* Register rw_pwm1_data, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pwm1_data;
#define REG_RD_ADDR_gio_rw_pwm1_data 212
#define REG_WR_ADDR_gio_rw_pwm1_data 212

/* Register rw_pwm2_ctrl, scope gio, type rw */
typedef struct {
  unsigned int mode         : 2;
  unsigned int ccd_override : 1;
  unsigned int ccd_val      : 1;
  unsigned int dummy1       : 28;
} reg_gio_rw_pwm2_ctrl;
#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216

/* Register rw_pwm2_var, scope gio, type rw */
typedef struct {
  unsigned int lo : 13;
  unsigned int hi : 13;
  unsigned int dummy1 : 6;
} reg_gio_rw_pwm2_var;
#define REG_RD_ADDR_gio_rw_pwm2_var 220
#define REG_WR_ADDR_gio_rw_pwm2_var 220

/* Register rw_pwm2_data, scope gio, type rw */
typedef struct {
  unsigned int data : 8;
  unsigned int dummy1 : 24;
} reg_gio_rw_pwm2_data;
#define REG_RD_ADDR_gio_rw_pwm2_data 224
#define REG_WR_ADDR_gio_rw_pwm2_data 224

/* Register rw_pwm_in_cfg, scope gio, type rw */
typedef struct {
  unsigned int pin : 3;
  unsigned int dummy1 : 29;
} reg_gio_rw_pwm_in_cfg;
#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228

/* Register r_pwm_in_lo, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pwm_in_lo;
#define REG_RD_ADDR_gio_r_pwm_in_lo 232

/* Register r_pwm_in_hi, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pwm_in_hi;
#define REG_RD_ADDR_gio_r_pwm_in_hi 236

/* Register r_pwm_in_cnt, scope gio, type r */
typedef struct {
  unsigned int data : 32;
} reg_gio_r_pwm_in_cnt;
#define REG_RD_ADDR_gio_r_pwm_in_cnt 240


/* Constants */
enum {
  regk_gio_anyedge                         = 0x00000007,
  regk_gio_f100k                           = 0x00000000,
  regk_gio_f1562                           = 0x00000000,
  regk_gio_f195                            = 0x00000003,
  regk_gio_f1m                             = 0x00000002,
  regk_gio_f390                            = 0x00000002,
  regk_gio_f400k                           = 0x00000001,
  regk_gio_f5m                             = 0x00000003,
  regk_gio_f781                            = 0x00000001,
  regk_gio_hi                              = 0x00000001,
  regk_gio_in                              = 0x00000000,
  regk_gio_intr_pa0                        = 0x00000000,
  regk_gio_intr_pa1                        = 0x00000000,
  regk_gio_intr_pa10                       = 0x00000001,
  regk_gio_intr_pa11                       = 0x00000001,
  regk_gio_intr_pa12                       = 0x00000001,
  regk_gio_intr_pa13                       = 0x00000001,
  regk_gio_intr_pa14                       = 0x00000001,
  regk_gio_intr_pa15                       = 0x00000001,
  regk_gio_intr_pa16                       = 0x00000002,
  regk_gio_intr_pa17                       = 0x00000002,
  regk_gio_intr_pa18                       = 0x00000002,
  regk_gio_intr_pa19                       = 0x00000002,
  regk_gio_intr_pa2                        = 0x00000000,
  regk_gio_intr_pa20                       = 0x00000002,
  regk_gio_intr_pa21                       = 0x00000002,
  regk_gio_intr_pa22                       = 0x00000002,
  regk_gio_intr_pa23                       = 0x00000002,
  regk_gio_intr_pa24                       = 0x00000003,
  regk_gio_intr_pa25                       = 0x00000003,
  regk_gio_intr_pa26                       = 0x00000003,
  regk_gio_intr_pa27                       = 0x00000003,
  regk_gio_intr_pa28                       = 0x00000003,
  regk_gio_intr_pa29                       = 0x00000003,
  regk_gio_intr_pa3                        = 0x00000000,
  regk_gio_intr_pa30                       = 0x00000003,
  regk_gio_intr_pa31                       = 0x00000003,
  regk_gio_intr_pa4                        = 0x00000000,
  regk_gio_intr_pa5                        = 0x00000000,
  regk_gio_intr_pa6                        = 0x00000000,
  regk_gio_intr_pa7                        = 0x00000000,
  regk_gio_intr_pa8                        = 0x00000001,
  regk_gio_intr_pa9                        = 0x00000001,
  regk_gio_intr_pb0                        = 0x00000004,
  regk_gio_intr_pb1                        = 0x00000004,
  regk_gio_intr_pb10                       = 0x00000005,
  regk_gio_intr_pb11                       = 0x00000005,
  regk_gio_intr_pb12                       = 0x00000005,
  regk_gio_intr_pb13                       = 0x00000005,
  regk_gio_intr_pb14                       = 0x00000005,
  regk_gio_intr_pb15                       = 0x00000005,
  regk_gio_intr_pb16                       = 0x00000006,
  regk_gio_intr_pb17                       = 0x00000006,
  regk_gio_intr_pb18                       = 0x00000006,
  regk_gio_intr_pb19                       = 0x00000006,
  regk_gio_intr_pb2                        = 0x00000004,
  regk_gio_intr_pb20                       = 0x00000006,
  regk_gio_intr_pb21                       = 0x00000006,
  regk_gio_intr_pb22                       = 0x00000006,
  regk_gio_intr_pb23                       = 0x00000006,
  regk_gio_intr_pb24                       = 0x00000007,
  regk_gio_intr_pb25                       = 0x00000007,
  regk_gio_intr_pb26                       = 0x00000007,
  regk_gio_intr_pb27                       = 0x00000007,
  regk_gio_intr_pb28                       = 0x00000007,
  regk_gio_intr_pb29                       = 0x00000007,
  regk_gio_intr_pb3                        = 0x00000004,
  regk_gio_intr_pb30                       = 0x00000007,
  regk_gio_intr_pb31                       = 0x00000007,
  regk_gio_intr_pb4                        = 0x00000004,
  regk_gio_intr_pb5                        = 0x00000004,
  regk_gio_intr_pb6                        = 0x00000004,
  regk_gio_intr_pb7                        = 0x00000004,
  regk_gio_intr_pb8                        = 0x00000005,
  regk_gio_intr_pb9                        = 0x00000005,
  regk_gio_intr_pc0                        = 0x00000008,
  regk_gio_intr_pc1                        = 0x00000008,
  regk_gio_intr_pc10                       = 0x00000009,
  regk_gio_intr_pc11                       = 0x00000009,
  regk_gio_intr_pc12                       = 0x00000009,
  regk_gio_intr_pc13                       = 0x00000009,
  regk_gio_intr_pc14                       = 0x00000009,
  regk_gio_intr_pc15                       = 0x00000009,
  regk_gio_intr_pc2                        = 0x00000008,
  regk_gio_intr_pc3                        = 0x00000008,
  regk_gio_intr_pc4                        = 0x00000008,
  regk_gio_intr_pc5                        = 0x00000008,
  regk_gio_intr_pc6                        = 0x00000008,
  regk_gio_intr_pc7                        = 0x00000008,
  regk_gio_intr_pc8                        = 0x00000009,
  regk_gio_intr_pc9                        = 0x00000009,
  regk_gio_intr_pd0                        = 0x0000000c,
  regk_gio_intr_pd1                        = 0x0000000c,
  regk_gio_intr_pd10                       = 0x0000000d,
  regk_gio_intr_pd11                       = 0x0000000d,
  regk_gio_intr_pd12                       = 0x0000000d,
  regk_gio_intr_pd13                       = 0x0000000d,
  regk_gio_intr_pd14                       = 0x0000000d,
  regk_gio_intr_pd15                       = 0x0000000d,
  regk_gio_intr_pd16                       = 0x0000000e,
  regk_gio_intr_pd17                       = 0x0000000e,
  regk_gio_intr_pd18                       = 0x0000000e,
  regk_gio_intr_pd19                       = 0x0000000e,
  regk_gio_intr_pd2                        = 0x0000000c,
  regk_gio_intr_pd20                       = 0x0000000e,
  regk_gio_intr_pd21                       = 0x0000000e,
  regk_gio_intr_pd22                       = 0x0000000e,
  regk_gio_intr_pd23                       = 0x0000000e,
  regk_gio_intr_pd24                       = 0x0000000f,
  regk_gio_intr_pd25                       = 0x0000000f,
  regk_gio_intr_pd26                       = 0x0000000f,
  regk_gio_intr_pd27                       = 0x0000000f,
  regk_gio_intr_pd28                       = 0x0000000f,
  regk_gio_intr_pd29                       = 0x0000000f,
  regk_gio_intr_pd3                        = 0x0000000c,
  regk_gio_intr_pd30                       = 0x0000000f,
  regk_gio_intr_pd31                       = 0x0000000f,
  regk_gio_intr_pd4                        = 0x0000000c,
  regk_gio_intr_pd5                        = 0x0000000c,
  regk_gio_intr_pd6                        = 0x0000000c,
  regk_gio_intr_pd7                        = 0x0000000c,
  regk_gio_intr_pd8                        = 0x0000000d,
  regk_gio_intr_pd9                        = 0x0000000d,
  regk_gio_lo                              = 0x00000002,
  regk_gio_lsb                             = 0x00000000,
  regk_gio_msb                             = 0x00000001,
  regk_gio_negedge                         = 0x00000006,
  regk_gio_no                              = 0x00000000,
  regk_gio_no_switch                       = 0x0000003f,
  regk_gio_none                            = 0x00000007,
  regk_gio_off                             = 0x00000000,
  regk_gio_opendrain                       = 0x00000000,
  regk_gio_out                             = 0x00000001,
  regk_gio_posedge                         = 0x00000005,
  regk_gio_pwm_hfp                         = 0x00000002,
  regk_gio_pwm_pa0                         = 0x00000001,
  regk_gio_pwm_pa19                        = 0x00000004,
  regk_gio_pwm_pa6                         = 0x00000002,
  regk_gio_pwm_pa7                         = 0x00000003,
  regk_gio_pwm_pb26                        = 0x00000005,
  regk_gio_pwm_pd23                        = 0x00000006,
  regk_gio_pwm_pd31                        = 0x00000007,
  regk_gio_pwm_std                         = 0x00000001,
  regk_gio_pwm_var                         = 0x00000003,
  regk_gio_rw_i2c0_cfg_default             = 0x00000020,
  regk_gio_rw_i2c0_ctrl_default            = 0x00010000,
  regk_gio_rw_i2c0_start_default           = 0x00000000,
  regk_gio_rw_i2c1_cfg_default             = 0x00000aa0,
  regk_gio_rw_i2c1_ctrl_default            = 0x00010000,
  regk_gio_rw_i2c1_start_default           = 0x00000000,
  regk_gio_rw_intr_cfg_default             = 0x00000000,
  regk_gio_rw_intr_mask_default            = 0x00000000,
  regk_gio_rw_pa_oe_default                = 0x00000000,
  regk_gio_rw_pb_oe_default                = 0x00000000,
  regk_gio_rw_pc_oe_default                = 0x00000000,
  regk_gio_rw_ppwm_data_default            = 0x00000000,
  regk_gio_rw_pwm0_ctrl_default            = 0x00000000,
  regk_gio_rw_pwm1_ctrl_default            = 0x00000000,
  regk_gio_rw_pwm2_ctrl_default            = 0x00000000,
  regk_gio_rw_pwm_in_cfg_default           = 0x00000000,
  regk_gio_sda0                            = 0x00000000,
  regk_gio_sda1                            = 0x00000001,
  regk_gio_sda2                            = 0x00000002,
  regk_gio_sda3                            = 0x00000003,
  regk_gio_sen                             = 0x00000000,
  regk_gio_set                             = 0x00000003,
  regk_gio_yes                             = 0x00000001
};
#endif /* __gio_defs_h */