config [31mCONFIG_IRQCHIP[0m
def_bool y
depends on [31mCONFIG_OF_IRQ[0m
config [31mCONFIG_ARM_GIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
config [31mCONFIG_ARM_GIC_PM[0m
bool
depends on [31mCONFIG_PM[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_PM_CLK[0m
config [31mCONFIG_ARM_GIC_MAX_NR[0m
int
default 2 if [31mCONFIG_ARCH_REALVIEW[0m
default 1
config [31mCONFIG_ARM_GIC_V2M[0m
bool
depends on [31mCONFIG_PCI[0m
select [31mCONFIG_ARM_GIC[0m
select [31mCONFIG_PCI_MSI[0m
config [31mCONFIG_GIC_NON_BANKED[0m
bool
config [31mCONFIG_ARM_GIC_V3[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_PARTITION_PERCPU[0m
config [31mCONFIG_ARM_GIC_V3_ITS[0m
bool
depends on [31mCONFIG_PCI[0m
depends on [31mCONFIG_PCI_MSI[0m
select [31mCONFIG_ACPI_IORT[0m if [31mCONFIG_ACPI[0m
config [31mCONFIG_ARM_NVIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_ARM_VIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
config [31mCONFIG_ARM_VIC_NR[0m
int
default 4 if [31mCONFIG_ARCH_S5PV210[0m
default 2
depends on [31mCONFIG_ARM_VIC[0m
help
The maximum number of VICs available in the system, for
power management.
config [31mCONFIG_ARMADA_370_XP_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_PCI_MSI[0m if [31mCONFIG_PCI[0m
config [31mCONFIG_ALPINE_MSI[0m
bool
depends on [31mCONFIG_PCI[0m
select [31mCONFIG_PCI_MSI[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_ATMEL_AIC_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_ATMEL_AIC5_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
config [31mCONFIG_I8259[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BCM6345_L1_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BCM7038_L1_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BCM7120_L2_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_BRCMSTB_L2_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_DW_APB_ICTL[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_HISILICON_IRQ_MBIGEN[0m
bool
select [31mCONFIG_ARM_GIC_V3[0m
select [31mCONFIG_ARM_GIC_V3_ITS[0m
config [31mCONFIG_IMGPDC_IRQ[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_IRQ_MIPS_CPU[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_CLPS711X_IRQCHIP[0m
bool
depends on [31mCONFIG_ARCH_CLPS711X[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
select [31mCONFIG_SPARSE_IRQ[0m
default y
config [31mCONFIG_OR1K_PIC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_OMAP_IRQCHIP[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_ORION_IRQCHIP[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_MULTI_IRQ_HANDLER[0m
config [31mCONFIG_PIC32_EVIC[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_JCORE_AIC[0m
bool "J-Core integrated AIC" if [31mCONFIG_COMPILE_TEST[0m
depends on [31mCONFIG_OF[0m
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support for the J-Core integrated AIC.
config [31mCONFIG_RENESAS_INTC_IRQPIN[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_RENESAS_IRQC[0m
bool
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_ST_IRQCHIP[0m
bool
select [31mCONFIG_REGMAP[0m
select [31mCONFIG_MFD_SYSCON[0m
help
Enables SysCfg Controlled IRQs on STi based platforms.
config [31mCONFIG_TANGO_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_TB10X_IRQC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_GENERIC_IRQ_CHIP[0m
config [31mCONFIG_TS4800_IRQ[0m
tristate "TS-4800 IRQ controller"
select [31mCONFIG_IRQ_DOMAIN[0m
depends on [31mCONFIG_HAS_IOMEM[0m
depends on [31mCONFIG_SOC_IMX51[0m || [31mCONFIG_COMPILE_TEST[0m
help
Support for the TS-4800 [31mCONFIG_FPGA[0m IRQ controller
config [31mCONFIG_VERSATILE_FPGA_IRQ[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_VERSATILE_FPGA_IRQ_NR[0m
int
default 4
depends on [31mCONFIG_VERSATILE_FPGA_IRQ[0m
config [31mCONFIG_XTENSA_MX[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_XILINX_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_IRQ_CROSSBAR[0m
bool
help
Support for a CROSSBAR ip that precedes the main interrupt controller.
The primary irqchip invokes the crossbar's callback which inturn allocates
a free irq and configures the IP. Thus the peripheral interrupts are
routed to one of the free irqchip interrupt lines.
config [31mCONFIG_KEYSTONE_IRQ[0m
tristate "Keystone 2 IRQ controller IP"
depends on [31mCONFIG_ARCH_KEYSTONE[0m
help
Support for Texas Instruments Keystone 2 IRQ controller IP which
is part of the Keystone 2 IPC mechanism
config [31mCONFIG_MIPS_GIC[0m
bool
select [31mCONFIG_GENERIC_IRQ_IPI[0m
select [31mCONFIG_IRQ_DOMAIN_HIERARCHY[0m
select [31mCONFIG_MIPS_CM[0m
config [31mCONFIG_INGENIC_IRQ[0m
bool
depends on [31mCONFIG_MACH_INGENIC[0m
default y
config [31mCONFIG_RENESAS_H8300H_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_RENESAS_H8S_INTC[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
config [31mCONFIG_IMX_GPCV2[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m
help
Enables the wakeup IRQs for IMX platforms with GPCv2 block
config [31mCONFIG_IRQ_MXS[0m
def_bool y if [31mCONFIG_MACH_ASM9260[0m || [31mCONFIG_ARCH_MXS[0m
select [31mCONFIG_IRQ_DOMAIN[0m
select [31mCONFIG_STMP_DEVICE[0m
config [31mCONFIG_MVEBU_ODMI[0m
bool
config [31mCONFIG_MVEBU_PIC[0m
bool
config [31mCONFIG_LS_SCFG_MSI[0m
def_bool y if [31mCONFIG_SOC_LS1021A[0m || [31mCONFIG_ARCH_LAYERSCAPE[0m
depends on [31mCONFIG_PCI[0m && [31mCONFIG_PCI_MSI[0m
config [31mCONFIG_PARTITION_PERCPU[0m
bool
config [31mCONFIG_EZNPS_GIC[0m
bool "NPS400 Global Interrupt Manager (GIM)"
depends on [31mCONFIG_ARC[0m || ([31mCONFIG_COMPILE_TEST[0m && ![31mCONFIG_64BIT[0m)
select [31mCONFIG_IRQ_DOMAIN[0m
help
Support the EZchip NPS400 global interrupt controller
config [31mCONFIG_STM32_EXTI[0m
bool
select [31mCONFIG_IRQ_DOMAIN[0m