1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 | /* * Static Memory Controller for AT32 chips * * Copyright (C) 2006 Atmel Corporation * * Inspired by the OMAP2 General-Purpose Memory Controller interface * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __ARCH_AT32AP_SMC_H #define __ARCH_AT32AP_SMC_H /* * All timing parameters are in nanoseconds. */ struct smc_timing { /* Delay from address valid to assertion of given strobe */ int ncs_read_setup; int nrd_setup; int ncs_write_setup; int nwe_setup; /* Pulse length of given strobe */ int ncs_read_pulse; int nrd_pulse; int ncs_write_pulse; int nwe_pulse; /* Total cycle length of given operation */ int read_cycle; int write_cycle; /* Minimal recovery times, will extend cycle if needed */ int ncs_read_recover; int nrd_recover; int ncs_write_recover; int nwe_recover; }; /* * All timing parameters are in clock cycles. */ struct smc_config { /* Delay from address valid to assertion of given strobe */ u8 ncs_read_setup; u8 nrd_setup; u8 ncs_write_setup; u8 nwe_setup; /* Pulse length of given strobe */ u8 ncs_read_pulse; u8 nrd_pulse; u8 ncs_write_pulse; u8 nwe_pulse; /* Total cycle length of given operation */ u8 read_cycle; u8 write_cycle; /* Bus width in bytes */ u8 bus_width; /* * 0: Data is sampled on rising edge of NCS * 1: Data is sampled on rising edge of NRD */ unsigned int nrd_controlled:1; /* * 0: Data is driven on falling edge of NCS * 1: Data is driven on falling edge of NWR */ unsigned int nwe_controlled:1; /* * 0: NWAIT is disabled * 1: Reserved * 2: NWAIT is frozen mode * 3: NWAIT in ready mode */ unsigned int nwait_mode:2; /* * 0: Byte select access type * 1: Byte write access type */ unsigned int byte_write:1; /* * Number of clock cycles before data is released after * the rising edge of the read controlling signal * * Total cycles from SMC is tdf_cycles + 1 */ unsigned int tdf_cycles:4; /* * 0: TDF optimization disabled * 1: TDF optimization enabled */ unsigned int tdf_mode:1; }; extern void smc_set_timing(struct smc_config *config, const struct smc_timing *timing); extern int smc_set_configuration(int cs, const struct smc_config *config); extern struct smc_config *smc_get_configuration(int cs); #endif /* __ARCH_AT32AP_SMC_H */ |