1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 | /* * Copyright 2007-2009 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ #ifndef __MACH_BF548_H__ #define __MACH_BF548_H__ #define OFFSET_(x) ((x) & 0x0000FFFF) /*some misc defines*/ #define IMASK_IVG15 0x8000 #define IMASK_IVG14 0x4000 #define IMASK_IVG13 0x2000 #define IMASK_IVG12 0x1000 #define IMASK_IVG11 0x0800 #define IMASK_IVG10 0x0400 #define IMASK_IVG9 0x0200 #define IMASK_IVG8 0x0100 #define IMASK_IVG7 0x0080 #define IMASK_IVGTMR 0x0040 #define IMASK_IVGHW 0x0020 /***************************/ #define BFIN_DSUBBANKS 4 #define BFIN_DWAYS 2 #define BFIN_DLINES 64 #define BFIN_ISUBBANKS 4 #define BFIN_IWAYS 4 #define BFIN_ILINES 32 #define WAY0_L 0x1 #define WAY1_L 0x2 #define WAY01_L 0x3 #define WAY2_L 0x4 #define WAY02_L 0x5 #define WAY12_L 0x6 #define WAY012_L 0x7 #define WAY3_L 0x8 #define WAY03_L 0x9 #define WAY13_L 0xA #define WAY013_L 0xB #define WAY32_L 0xC #define WAY320_L 0xD #define WAY321_L 0xE #define WAYALL_L 0xF #define DMC_ENABLE (2<<2) /*yes, 2, not 1 */ /********************************* EBIU Settings ************************************/ #define AMBCTL0VAL (([31mCONFIG_BANK_1[0m << 16) | [31mCONFIG_BANK_0[0m) #define AMBCTL1VAL (([31mCONFIG_BANK_3[0m << 16) | [31mCONFIG_BANK_2[0m) #ifdef [31mCONFIG_C_AMBEN_ALL[0m #define V_AMBEN AMBEN_ALL #endif #ifdef [31mCONFIG_C_AMBEN[0m #define V_AMBEN 0x0 #endif #ifdef [31mCONFIG_C_AMBEN_B0[0m #define V_AMBEN AMBEN_B0 #endif #ifdef [31mCONFIG_C_AMBEN_B0_B1[0m #define V_AMBEN AMBEN_B0_B1 #endif #ifdef [31mCONFIG_C_AMBEN_B0_B1_B2[0m #define V_AMBEN AMBEN_B0_B1_B2 #endif #ifdef [31mCONFIG_C_AMCKEN[0m #define V_AMCKEN AMCKEN #else #define V_AMCKEN 0x0 #endif #define AMGCTLVAL (V_AMBEN | V_AMCKEN) #if defined([31mCONFIG_BF542[0m) # define CPU "BF542" # define CPUID 0x27de #elif defined([31mCONFIG_BF544[0m) # define CPU "BF544" # define CPUID 0x27de #elif defined([31mCONFIG_BF547[0m) # define CPU "BF547" # define CPUID 0x27de #elif defined([31mCONFIG_BF548[0m) # define CPU "BF548" # define CPUID 0x27de #elif defined([31mCONFIG_BF549[0m) # define CPU "BF549" # define CPUID 0x27de #endif #ifndef CPU #error "Unknown CPU type - This kernel doesn't seem to be configured properly" #endif #endif /* __MACH_BF48_H__ */ |