config [31mCONFIG_PPC_CELL[0m
bool
default n
config [31mCONFIG_PPC_CELL_COMMON[0m
bool
select [31mCONFIG_PPC_CELL[0m
select [31mCONFIG_PPC_DCR_MMIO[0m
select [31mCONFIG_PPC_INDIRECT_PIO[0m
select [31mCONFIG_PPC_INDIRECT_MMIO[0m
select [31mCONFIG_PPC_NATIVE[0m
select [31mCONFIG_PPC_RTAS[0m
select [31mCONFIG_IRQ_EDGE_EOI_HANDLER[0m
config [31mCONFIG_PPC_CELL_NATIVE[0m
bool
select [31mCONFIG_PPC_CELL_COMMON[0m
select [31mCONFIG_MPIC[0m
select [31mCONFIG_PPC_IO_WORKAROUNDS[0m
select [31mCONFIG_IBM_EMAC_EMAC4[0m if [31mCONFIG_IBM_EMAC[0m
select [31mCONFIG_IBM_EMAC_RGMII[0m if [31mCONFIG_IBM_EMAC[0m
select [31mCONFIG_IBM_EMAC_ZMII[0m if [31mCONFIG_IBM_EMAC[0m #test only
select [31mCONFIG_IBM_EMAC_TAH[0m if [31mCONFIG_IBM_EMAC[0m #test only
default n
config [31mCONFIG_PPC_IBM_CELL_BLADE[0m
bool "IBM Cell Blade"
depends on [31mCONFIG_PPC64[0m && [31mCONFIG_PPC_BOOK3S[0m && [31mCONFIG_CPU_BIG_ENDIAN[0m
select [31mCONFIG_PPC_CELL_NATIVE[0m
select [31mCONFIG_PPC_OF_PLATFORM_PCI[0m
select [31mCONFIG_PCI[0m
select [31mCONFIG_MMIO_NVRAM[0m
select [31mCONFIG_PPC_UDBG_16550[0m
select [31mCONFIG_UDBG_RTAS_CONSOLE[0m
config [31mCONFIG_AXON_MSI[0m
bool
depends on [31mCONFIG_PPC_IBM_CELL_BLADE[0m && [31mCONFIG_PCI_MSI[0m
default y
menu "Cell Broadband Engine options"
depends on [31mCONFIG_PPC_CELL[0m
config [31mCONFIG_SPU_FS[0m
tristate "SPU file system"
default m
depends on [31mCONFIG_PPC_CELL[0m
select [31mCONFIG_SPU_BASE[0m
help
The SPU file system is used to access Synergistic Processing
Units on machines implementing the Broadband Processor
Architecture.
config [31mCONFIG_SPU_BASE[0m
bool
default n
select [31mCONFIG_PPC_COPRO_BASE[0m
config [31mCONFIG_CBE_RAS[0m
bool "RAS features for bare metal Cell BE"
depends on [31mCONFIG_PPC_CELL_NATIVE[0m
default y
config [31mCONFIG_PPC_IBM_CELL_RESETBUTTON[0m
bool "IBM Cell Blade Pinhole reset button"
depends on [31mCONFIG_CBE_RAS[0m && [31mCONFIG_PPC_IBM_CELL_BLADE[0m
default y
help
Support Pinhole Resetbutton on IBM Cell blades.
This adds a method to trigger system reset via front panel pinhole button.
config [31mCONFIG_PPC_IBM_CELL_POWERBUTTON[0m
tristate "IBM Cell Blade power button"
depends on [31mCONFIG_PPC_IBM_CELL_BLADE[0m && [31mCONFIG_INPUT_EVDEV[0m
default y
help
Support Powerbutton on IBM Cell blades.
This will enable the powerbutton as an input device.
config [31mCONFIG_CBE_THERM[0m
tristate "CBE thermal support"
default m
depends on [31mCONFIG_CBE_RAS[0m && [31mCONFIG_SPU_BASE[0m
config [31mCONFIG_PPC_PMI[0m
tristate
default y
depends on [31mCONFIG_CPU_FREQ_CBE_PMI[0m || [31mCONFIG_PPC_IBM_CELL_POWERBUTTON[0m
help
PMI (Platform Management Interrupt) is a way to
communicate with the BMC (Baseboard Management Controller).
It is used in some IBM Cell blades.
config [31mCONFIG_CBE_CPUFREQ_SPU_GOVERNOR[0m
tristate "CBE frequency scaling based on SPU usage"
depends on [31mCONFIG_SPU_FS[0m && [31mCONFIG_CPU_FREQ[0m
default m
help
This governor checks for spu usage to adjust the cpu frequency.
If no spu is running on a given cpu, that cpu will be throttled to
the minimal possible frequency.
endmenu
config [31mCONFIG_OPROFILE_CELL[0m
def_bool y
depends on [31mCONFIG_PPC_CELL_NATIVE[0m && ([31mCONFIG_OPROFILE[0m = m || [31mCONFIG_OPROFILE[0m = y) && [31mCONFIG_SPU_BASE[0m