1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 | /* * Copyright 2011 Tilera Corporation. All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * as published by the Free Software Foundation, version 2. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or * NON INFRINGEMENT. See the GNU General Public License for * more details. */ #ifndef __ARCH_INTERRUPTS_H__ #define __ARCH_INTERRUPTS_H__ #ifndef __KERNEL__ /** Mask for an interrupt. */ #ifdef __ASSEMBLER__ /* Note: must handle breaking interrupts into high and low words manually. */ #define INT_MASK(intno) (1 << (intno)) #else #define INT_MASK(intno) (1ULL << (intno)) #endif #endif /** Where a given interrupt executes */ #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8)) /** Where to store a vector for a given interrupt. */ #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0) /** The base address of user-level interrupts. */ #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0) /** Additional synthetic interrupt. */ #define INT_BREAKPOINT (63) #define INT_MEM_ERROR 0 #define INT_SINGLE_STEP_3 1 #define INT_SINGLE_STEP_2 2 #define INT_SINGLE_STEP_1 3 #define INT_SINGLE_STEP_0 4 #define INT_IDN_COMPLETE 5 #define INT_UDN_COMPLETE 6 #define INT_ITLB_MISS 7 #define INT_ILL 8 #define INT_GPV 9 #define INT_IDN_ACCESS 10 #define INT_UDN_ACCESS 11 #define INT_SWINT_3 12 #define INT_SWINT_2 13 #define INT_SWINT_1 14 #define INT_SWINT_0 15 #define INT_ILL_TRANS 16 #define INT_UNALIGN_DATA 17 #define INT_DTLB_MISS 18 #define INT_DTLB_ACCESS 19 #define INT_IDN_FIREWALL 20 #define INT_UDN_FIREWALL 21 #define INT_TILE_TIMER 22 #define INT_AUX_TILE_TIMER 23 #define INT_IDN_TIMER 24 #define INT_UDN_TIMER 25 #define INT_IDN_AVAIL 26 #define INT_UDN_AVAIL 27 #define INT_IPI_3 28 #define INT_IPI_2 29 #define INT_IPI_1 30 #define INT_IPI_0 31 #define INT_PERF_COUNT 32 #define INT_AUX_PERF_COUNT 33 #define INT_INTCTRL_3 34 #define INT_INTCTRL_2 35 #define INT_INTCTRL_1 36 #define INT_INTCTRL_0 37 #define INT_BOOT_ACCESS 38 #define INT_WORLD_ACCESS 39 #define INT_I_ASID 40 #define INT_D_ASID 41 #define INT_DOUBLE_FAULT 42 #define NUM_INTERRUPTS 43 #ifndef __ASSEMBLER__ #define QUEUED_INTERRUPTS ( \ (1ULL << INT_MEM_ERROR) | \ (1ULL << INT_IDN_COMPLETE) | \ (1ULL << INT_UDN_COMPLETE) | \ (1ULL << INT_IDN_FIREWALL) | \ (1ULL << INT_UDN_FIREWALL) | \ (1ULL << INT_TILE_TIMER) | \ (1ULL << INT_AUX_TILE_TIMER) | \ (1ULL << INT_IDN_TIMER) | \ (1ULL << INT_UDN_TIMER) | \ (1ULL << INT_IDN_AVAIL) | \ (1ULL << INT_UDN_AVAIL) | \ (1ULL << INT_IPI_3) | \ (1ULL << INT_IPI_2) | \ (1ULL << INT_IPI_1) | \ (1ULL << INT_IPI_0) | \ (1ULL << INT_PERF_COUNT) | \ (1ULL << INT_AUX_PERF_COUNT) | \ (1ULL << INT_INTCTRL_3) | \ (1ULL << INT_INTCTRL_2) | \ (1ULL << INT_INTCTRL_1) | \ (1ULL << INT_INTCTRL_0) | \ (1ULL << INT_BOOT_ACCESS) | \ (1ULL << INT_WORLD_ACCESS) | \ (1ULL << INT_I_ASID) | \ (1ULL << INT_D_ASID) | \ (1ULL << INT_DOUBLE_FAULT) | \ 0) #define NONQUEUED_INTERRUPTS ( \ (1ULL << INT_SINGLE_STEP_3) | \ (1ULL << INT_SINGLE_STEP_2) | \ (1ULL << INT_SINGLE_STEP_1) | \ (1ULL << INT_SINGLE_STEP_0) | \ (1ULL << INT_ITLB_MISS) | \ (1ULL << INT_ILL) | \ (1ULL << INT_GPV) | \ (1ULL << INT_IDN_ACCESS) | \ (1ULL << INT_UDN_ACCESS) | \ (1ULL << INT_SWINT_3) | \ (1ULL << INT_SWINT_2) | \ (1ULL << INT_SWINT_1) | \ (1ULL << INT_SWINT_0) | \ (1ULL << INT_ILL_TRANS) | \ (1ULL << INT_UNALIGN_DATA) | \ (1ULL << INT_DTLB_MISS) | \ (1ULL << INT_DTLB_ACCESS) | \ 0) #define CRITICAL_MASKED_INTERRUPTS ( \ (1ULL << INT_MEM_ERROR) | \ (1ULL << INT_SINGLE_STEP_3) | \ (1ULL << INT_SINGLE_STEP_2) | \ (1ULL << INT_SINGLE_STEP_1) | \ (1ULL << INT_SINGLE_STEP_0) | \ (1ULL << INT_IDN_COMPLETE) | \ (1ULL << INT_UDN_COMPLETE) | \ (1ULL << INT_IDN_FIREWALL) | \ (1ULL << INT_UDN_FIREWALL) | \ (1ULL << INT_TILE_TIMER) | \ (1ULL << INT_AUX_TILE_TIMER) | \ (1ULL << INT_IDN_TIMER) | \ (1ULL << INT_UDN_TIMER) | \ (1ULL << INT_IDN_AVAIL) | \ (1ULL << INT_UDN_AVAIL) | \ (1ULL << INT_IPI_3) | \ (1ULL << INT_IPI_2) | \ (1ULL << INT_IPI_1) | \ (1ULL << INT_IPI_0) | \ (1ULL << INT_PERF_COUNT) | \ (1ULL << INT_AUX_PERF_COUNT) | \ (1ULL << INT_INTCTRL_3) | \ (1ULL << INT_INTCTRL_2) | \ (1ULL << INT_INTCTRL_1) | \ (1ULL << INT_INTCTRL_0) | \ 0) #define CRITICAL_UNMASKED_INTERRUPTS ( \ (1ULL << INT_ITLB_MISS) | \ (1ULL << INT_ILL) | \ (1ULL << INT_GPV) | \ (1ULL << INT_IDN_ACCESS) | \ (1ULL << INT_UDN_ACCESS) | \ (1ULL << INT_SWINT_3) | \ (1ULL << INT_SWINT_2) | \ (1ULL << INT_SWINT_1) | \ (1ULL << INT_SWINT_0) | \ (1ULL << INT_ILL_TRANS) | \ (1ULL << INT_UNALIGN_DATA) | \ (1ULL << INT_DTLB_MISS) | \ (1ULL << INT_DTLB_ACCESS) | \ (1ULL << INT_BOOT_ACCESS) | \ (1ULL << INT_WORLD_ACCESS) | \ (1ULL << INT_I_ASID) | \ (1ULL << INT_D_ASID) | \ (1ULL << INT_DOUBLE_FAULT) | \ 0) #define MASKABLE_INTERRUPTS ( \ (1ULL << INT_MEM_ERROR) | \ (1ULL << INT_SINGLE_STEP_3) | \ (1ULL << INT_SINGLE_STEP_2) | \ (1ULL << INT_SINGLE_STEP_1) | \ (1ULL << INT_SINGLE_STEP_0) | \ (1ULL << INT_IDN_COMPLETE) | \ (1ULL << INT_UDN_COMPLETE) | \ (1ULL << INT_IDN_FIREWALL) | \ (1ULL << INT_UDN_FIREWALL) | \ (1ULL << INT_TILE_TIMER) | \ (1ULL << INT_AUX_TILE_TIMER) | \ (1ULL << INT_IDN_TIMER) | \ (1ULL << INT_UDN_TIMER) | \ (1ULL << INT_IDN_AVAIL) | \ (1ULL << INT_UDN_AVAIL) | \ (1ULL << INT_IPI_3) | \ (1ULL << INT_IPI_2) | \ (1ULL << INT_IPI_1) | \ (1ULL << INT_IPI_0) | \ (1ULL << INT_PERF_COUNT) | \ (1ULL << INT_AUX_PERF_COUNT) | \ (1ULL << INT_INTCTRL_3) | \ (1ULL << INT_INTCTRL_2) | \ (1ULL << INT_INTCTRL_1) | \ (1ULL << INT_INTCTRL_0) | \ 0) #define UNMASKABLE_INTERRUPTS ( \ (1ULL << INT_ITLB_MISS) | \ (1ULL << INT_ILL) | \ (1ULL << INT_GPV) | \ (1ULL << INT_IDN_ACCESS) | \ (1ULL << INT_UDN_ACCESS) | \ (1ULL << INT_SWINT_3) | \ (1ULL << INT_SWINT_2) | \ (1ULL << INT_SWINT_1) | \ (1ULL << INT_SWINT_0) | \ (1ULL << INT_ILL_TRANS) | \ (1ULL << INT_UNALIGN_DATA) | \ (1ULL << INT_DTLB_MISS) | \ (1ULL << INT_DTLB_ACCESS) | \ (1ULL << INT_BOOT_ACCESS) | \ (1ULL << INT_WORLD_ACCESS) | \ (1ULL << INT_I_ASID) | \ (1ULL << INT_D_ASID) | \ (1ULL << INT_DOUBLE_FAULT) | \ 0) #define SYNC_INTERRUPTS ( \ (1ULL << INT_SINGLE_STEP_3) | \ (1ULL << INT_SINGLE_STEP_2) | \ (1ULL << INT_SINGLE_STEP_1) | \ (1ULL << INT_SINGLE_STEP_0) | \ (1ULL << INT_IDN_COMPLETE) | \ (1ULL << INT_UDN_COMPLETE) | \ (1ULL << INT_ITLB_MISS) | \ (1ULL << INT_ILL) | \ (1ULL << INT_GPV) | \ (1ULL << INT_IDN_ACCESS) | \ (1ULL << INT_UDN_ACCESS) | \ (1ULL << INT_SWINT_3) | \ (1ULL << INT_SWINT_2) | \ (1ULL << INT_SWINT_1) | \ (1ULL << INT_SWINT_0) | \ (1ULL << INT_ILL_TRANS) | \ (1ULL << INT_UNALIGN_DATA) | \ (1ULL << INT_DTLB_MISS) | \ (1ULL << INT_DTLB_ACCESS) | \ 0) #define NON_SYNC_INTERRUPTS ( \ (1ULL << INT_MEM_ERROR) | \ (1ULL << INT_IDN_FIREWALL) | \ (1ULL << INT_UDN_FIREWALL) | \ (1ULL << INT_TILE_TIMER) | \ (1ULL << INT_AUX_TILE_TIMER) | \ (1ULL << INT_IDN_TIMER) | \ (1ULL << INT_UDN_TIMER) | \ (1ULL << INT_IDN_AVAIL) | \ (1ULL << INT_UDN_AVAIL) | \ (1ULL << INT_IPI_3) | \ (1ULL << INT_IPI_2) | \ (1ULL << INT_IPI_1) | \ (1ULL << INT_IPI_0) | \ (1ULL << INT_PERF_COUNT) | \ (1ULL << INT_AUX_PERF_COUNT) | \ (1ULL << INT_INTCTRL_3) | \ (1ULL << INT_INTCTRL_2) | \ (1ULL << INT_INTCTRL_1) | \ (1ULL << INT_INTCTRL_0) | \ (1ULL << INT_BOOT_ACCESS) | \ (1ULL << INT_WORLD_ACCESS) | \ (1ULL << INT_I_ASID) | \ (1ULL << INT_D_ASID) | \ (1ULL << INT_DOUBLE_FAULT) | \ 0) #endif /* !__ASSEMBLER__ */ #endif /* !__ARCH_INTERRUPTS_H__ */ |