if [31mCONFIG_CPU_CAVIUM_OCTEON[0m config [31mCONFIG_CAVIUM_CN63XXP1[0m bool "Enable CN63XXP1 errata workarounds" default "n" help The CN63XXP1 chip requires build time workarounds to function reliably, select this option to enable them. These workarounds will cause a slight decrease in performance on non-CN63XXP1 hardware, so it is recommended to select "n" unless it is known the workarounds are needed. config [31mCONFIG_CAVIUM_OCTEON_CVMSEG_SIZE[0m int "Number of L1 cache lines reserved for CVMSEG memory" range 0 54 default 1 help CVMSEG LM is a segment that accesses portions of the dcache as a local memory; the larger CVMSEG is, the smaller the cache is. This selects the size of CVMSEG LM, which is in cache blocks. The legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is between zero and 6192 bytes). endif # [31mCONFIG_CPU_CAVIUM_OCTEON[0m if [31mCONFIG_CAVIUM_OCTEON_SOC[0m config [31mCONFIG_CAVIUM_OCTEON_2ND_KERNEL[0m bool "Build the kernel to be used as a 2nd kernel on the same chip" default "n" help This option configures this kernel to be linked at a different address and use the 2nd uart for output. This allows a kernel built with this option to be run at the same time as one built without this option. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m bool "Lock often used kernel code in the L2" default "y" help Enable locking parts of the kernel into the L2 cache. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2_TLB[0m bool "Lock the TLB handler in L2" depends on [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m default "y" help Lock the low level TLB fast path into L2. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION[0m bool "Lock the exception handler in L2" depends on [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m default "y" help Lock the low level exception handler into L2. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT[0m bool "Lock the interrupt handler in L2" depends on [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m default "y" help Lock the low level interrupt handler into L2. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT[0m bool "Lock the 2nd level interrupt handler in L2" depends on [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m default "y" help Lock the 2nd level interrupt handler in L2. config [31mCONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY[0m bool "Lock memcpy() in L2" depends on [31mCONFIG_CAVIUM_OCTEON_LOCK_L2[0m default "y" help Lock the kernel's implementation of memcpy() into L2. config [31mCONFIG_IOMMU_HELPER[0m bool config [31mCONFIG_NEED_SG_DMA_LENGTH[0m bool config [31mCONFIG_SWIOTLB[0m def_bool y select [31mCONFIG_IOMMU_HELPER[0m select [31mCONFIG_NEED_SG_DMA_LENGTH[0m config [31mCONFIG_OCTEON_ILM[0m tristate "Module to measure interrupt latency using Octeon CIU Timer" help This driver is a module to measure interrupt latency using the the CIU Timers on Octeon. To compile this driver as a module, choose [31mCONFIG_M[0m here. The module will be called octeon-ilm endif # [31mCONFIG_CAVIUM_OCTEON_SOC[0m |