#
# [31mCONFIG_EDAC[0m Kconfig
# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
# Licensed and distributed under the GPL
config [31mCONFIG_EDAC_ATOMIC_SCRUB[0m
bool
config [31mCONFIG_EDAC_SUPPORT[0m
bool
menuconfig [31mCONFIG_EDAC[0m
bool "EDAC (Error Detection And Correction) reporting"
depends on [31mCONFIG_HAS_IOMEM[0m && [31mCONFIG_EDAC_SUPPORT[0m
help
[31mCONFIG_EDAC[0m is designed to report errors in the core system.
These are low-level errors that are reported in the CPU or
supporting chipset or other subsystems:
memory errors, cache errors, [31mCONFIG_PCI[0m errors, thermal throttling, etc..
If unsure, select 'Y'.
If this code is reporting problems on your system, please
see the [31mCONFIG_EDAC[0m project web pages for more information at:
<http://bluesmoke.sourceforge.net/>
and:
<http://buttersideup.com/edacwiki>
There is also a mailing list for the [31mCONFIG_EDAC[0m project, which can
be found via the sourceforge page.
if [31mCONFIG_EDAC[0m
config [31mCONFIG_EDAC_LEGACY_SYSFS[0m
bool "EDAC legacy sysfs"
default y
help
Enable the compatibility sysfs nodes.
Use 'Y' if your edac utilities aren't ported to work with the newer
structures.
config [31mCONFIG_EDAC_DEBUG[0m
bool "Debugging"
help
This turns on debugging information for the entire [31mCONFIG_EDAC[0m subsystem.
You do so by inserting edac_module with "edac_debug_level=x." Valid
levels are 0-4 (from low to high) and by default it is set to 2.
Usually you should select 'N' here.
config [31mCONFIG_EDAC_DECODE_MCE[0m
tristate "Decode MCEs in human-readable form (only on AMD for now)"
depends on [31mCONFIG_CPU_SUP_AMD[0m && [31mCONFIG_X86_MCE_AMD[0m
default y
---help---
Enable this option if you want to decode Machine Check Exceptions
occurring on your machine in human-readable form.
You should definitely say Y here in case you want to decode MCEs
which occur really early upon boot, before the module infrastructure
has been initialized.
config [31mCONFIG_EDAC_MM_EDAC[0m
tristate "Main Memory EDAC (Error Detection And Correction) reporting"
select [31mCONFIG_RAS[0m
help
Some systems are able to detect and correct errors in main
memory. [31mCONFIG_EDAC[0m can report statistics on memory error
detection and correction ([31mCONFIG_EDAC[0m - or commonly referred to ECC
errors). [31mCONFIG_EDAC[0m will also try to decode where these errors
occurred so that a particular failing memory module can be
replaced. If unsure, select 'Y'.
config [31mCONFIG_EDAC_GHES[0m
bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
depends on [31mCONFIG_ACPI_APEI_GHES[0m && ([31mCONFIG_EDAC_MM_EDAC[0m=y)
default y
help
Not all machines support hardware-driven error report. Some of those
provide a BIOS-driven error report mechanism via [31mCONFIG_ACPI[0m, using the
APEI/GHES driver. By enabling this option, the error reports provided
by GHES are sent to userspace via the [31mCONFIG_EDAC[0m API.
When this option is enabled, it will disable the hardware-driven
mechanisms, if a GHES BIOS is detected, entering into the
"Firmware First" mode.
It should be noticed that keeping both GHES and a hardware-driven
error mechanism won't work well, as BIOS will race with OS, while
reading the error registers. So, if you want to not use "Firmware
first" GHES error mechanism, you should disable GHES either at
compilation time or by passing "ghes.disable=1" Kernel parameter
at boot time.
In doubt, say 'Y'.
config [31mCONFIG_EDAC_AMD64[0m
tristate "AMD64 (Opteron, Athlon64)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_AMD_NB[0m && [31mCONFIG_EDAC_DECODE_MCE[0m
help
Support for error detection and correction of DRAM ECC errors on
the AMD64 families (>= K8) of memory controllers.
config [31mCONFIG_EDAC_AMD64_ERROR_INJECTION[0m
bool "Sysfs HW Error injection facilities"
depends on [31mCONFIG_EDAC_AMD64[0m
help
Recent Opterons (Family 10h and later) provide for Memory Error
Injection into the ECC detection circuits. The amd64_edac module
allows the operator/user to inject Uncorrectable and Correctable
errors into DRAM.
When enabled, in each of the respective memory controller directories
(/sys/devices/system/edac/mc/mcX), there are 3 input files:
- inject_section (0..3, 16-byte section of 64-byte cacheline),
- inject_word (0..8, 16-bit word of 16-byte section),
- inject_ecc_vector (hex ecc vector: select bits of inject word)
In addition, there are two control files, inject_read and inject_write,
which trigger the DRAM ECC Read and Write respectively.
config [31mCONFIG_EDAC_AMD76X[0m
tristate "AMD 76x (760, 762, 768)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
help
Support for error detection and correction on the AMD 76x
series of chipsets used with the Athlon processor.
config [31mCONFIG_EDAC_E7XXX[0m
tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
help
Support for error detection and correction on the Intel
E7205, E7500, E7501 and E7505 server chipsets.
config [31mCONFIG_EDAC_E752X[0m
tristate "Intel e752x (e7520, e7525, e7320) and 3100"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
E7520, E7525, E7320 server chipsets.
config [31mCONFIG_EDAC_I82443BXGX[0m
tristate "Intel 82443BX/GX (440BX/GX)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
depends on [31mCONFIG_BROKEN[0m
help
Support for error detection and correction on the Intel
82443BX/GX memory controllers (440BX/GX chipsets).
config [31mCONFIG_EDAC_I82875P[0m
tristate "Intel 82875p (D82875P, E7210)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
help
Support for error detection and correction on the Intel
DP82785P and E7210 server chipsets.
config [31mCONFIG_EDAC_I82975X[0m
tristate "Intel 82975x (D82975x)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
DP82975x server chipsets.
config [31mCONFIG_EDAC_I3000[0m
tristate "Intel 3000/3010"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
3000 and 3010 server chipsets.
config [31mCONFIG_EDAC_I3200[0m
tristate "Intel 3200"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
3200 and 3210 server chipsets.
config [31mCONFIG_EDAC_IE31200[0m
tristate "Intel e312xx"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
E3-1200 based DRAM controllers.
config [31mCONFIG_EDAC_X38[0m
tristate "Intel X38"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction on the Intel
X38 server chipsets.
config [31mCONFIG_EDAC_I5400[0m
tristate "Intel 5400 (Seaburg) chipsets"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m
help
Support for error detection and correction the Intel
i5400 MCH chipset (Seaburg).
config [31mCONFIG_EDAC_I7CORE[0m
tristate "Intel i7 Core (Nehalem) processors"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86[0m && [31mCONFIG_X86_MCE_INTEL[0m
help
Support for error detection and correction the Intel
i7 Core (Nehalem) Integrated Memory Controller that exists on
newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
and Xeon 55xx processors.
config [31mCONFIG_EDAC_I82860[0m
tristate "Intel 82860"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
help
Support for error detection and correction on the Intel
82860 chipset.
config [31mCONFIG_EDAC_R82600[0m
tristate "Radisys 82600 embedded chipset"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_32[0m
help
Support for error detection and correction on the Radisys
82600 embedded chipset.
config [31mCONFIG_EDAC_I5000[0m
tristate "Intel Greencreek/Blackford chipset"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_X86[0m && [31mCONFIG_PCI[0m
help
Support for error detection and correction the Intel
Greekcreek/Blackford chipsets.
config [31mCONFIG_EDAC_I5100[0m
tristate "Intel San Clemente MCH"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_X86[0m && [31mCONFIG_PCI[0m
help
Support for error detection and correction the Intel
San Clemente MCH.
config [31mCONFIG_EDAC_I7300[0m
tristate "Intel Clarksboro MCH"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_X86[0m && [31mCONFIG_PCI[0m
help
Support for error detection and correction the Intel
Clarksboro MCH (Intel 7300 chipset).
config [31mCONFIG_EDAC_SBRIDGE[0m
tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_64[0m && [31mCONFIG_X86_MCE_INTEL[0m
depends on [31mCONFIG_PCI_MMCONFIG[0m
help
Support for error detection and correction the Intel
Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
config [31mCONFIG_EDAC_SKX[0m
tristate "Intel Skylake server Integrated MC"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_X86_64[0m && [31mCONFIG_X86_MCE_INTEL[0m
depends on [31mCONFIG_PCI_MMCONFIG[0m
help
Support for error detection and correction the Intel
Skylake server Integrated Memory Controllers.
config [31mCONFIG_EDAC_MPC85XX[0m
tristate "Freescale MPC83xx / MPC85xx"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_FSL_SOC[0m
help
Support for error detection and correction on the Freescale
MPC8349, MPC8560, MPC8540, MPC8548, T4240
config [31mCONFIG_EDAC_LAYERSCAPE[0m
tristate "Freescale Layerscape DDR"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_ARCH_LAYERSCAPE[0m
help
Support for error detection and correction on Freescale memory
controllers on Layerscape SoCs.
config [31mCONFIG_EDAC_MV64X60[0m
tristate "Marvell MV64x60"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_MV64X60[0m
help
Support for error detection and correction on the Marvell
MV64360 and MV64460 chipsets.
config [31mCONFIG_EDAC_PASEMI[0m
tristate "PA Semi PWRficient"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m
depends on [31mCONFIG_PPC_PASEMI[0m
help
Support for error detection and correction on PA Semi
PWRficient.
config [31mCONFIG_EDAC_CELL[0m
tristate "Cell Broadband Engine memory controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PPC_CELL_COMMON[0m
help
Support for error detection and correction on the
Cell Broadband Engine internal memory controller
on platform without a hypervisor
config [31mCONFIG_EDAC_PPC4XX[0m
tristate "PPC4xx IBM DDR2 Memory Controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_4xx[0m
help
This enables support for [31mCONFIG_EDAC[0m on the ECC memory used
with the IBM DDR2 memory controller found in various
PowerPC [31mCONFIG_4xx[0m embedded processors such as the [31mCONFIG_405EX[0m[r],
[31mCONFIG_440SP[0m, [31mCONFIG_440SPe[0m, [31mCONFIG_460EX[0m, 460GT and [31mCONFIG_460SX[0m.
config [31mCONFIG_EDAC_AMD8131[0m
tristate "AMD8131 HyperTransport PCI-X Tunnel"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_PPC_MAPLE[0m
help
Support for error detection and correction on the
AMD8131 HyperTransport [31mCONFIG_PCI[0m-X Tunnel chip.
Note, add more Kconfig dependency if it's adopted
on some machine other than Maple.
config [31mCONFIG_EDAC_AMD8111[0m
tristate "AMD8111 HyperTransport I/O Hub"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_PPC_MAPLE[0m
help
Support for error detection and correction on the
AMD8111 HyperTransport I/O Hub chip.
Note, add more Kconfig dependency if it's adopted
on some machine other than Maple.
config [31mCONFIG_EDAC_CPC925[0m
tristate "IBM CPC925 Memory Controller (PPC970FX)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PPC64[0m
help
Support for error detection and correction on the
IBM CPC925 Bridge and Memory Controller, which is
a companion chip to the PowerPC 970 family of
processors.
config [31mCONFIG_EDAC_TILE[0m
tristate "Tilera Memory Controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_TILE[0m
default y
help
Support for error detection and correction on the
Tilera memory controller.
config [31mCONFIG_EDAC_HIGHBANK_MC[0m
tristate "Highbank Memory Controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_ARCH_HIGHBANK[0m
help
Support for error detection and correction on the
Calxeda Highbank memory controller.
config [31mCONFIG_EDAC_HIGHBANK_L2[0m
tristate "Highbank L2 Cache"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_ARCH_HIGHBANK[0m
help
Support for error detection and correction on the
Calxeda Highbank memory controller.
config [31mCONFIG_EDAC_OCTEON_PC[0m
tristate "Cavium Octeon Primary Caches"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_CPU_CAVIUM_OCTEON[0m
help
Support for error detection and correction on the primary caches of
the cnMIPS cores of Cavium Octeon family SOCs.
config [31mCONFIG_EDAC_OCTEON_L2C[0m
tristate "Cavium Octeon Secondary Caches (L2C)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_CAVIUM_OCTEON_SOC[0m
help
Support for error detection and correction on the
Cavium Octeon family of SOCs.
config [31mCONFIG_EDAC_OCTEON_LMC[0m
tristate "Cavium Octeon DRAM Memory Controller (LMC)"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_CAVIUM_OCTEON_SOC[0m
help
Support for error detection and correction on the
Cavium Octeon family of SOCs.
config [31mCONFIG_EDAC_OCTEON_PCI[0m
tristate "Cavium Octeon PCI Controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_PCI[0m && [31mCONFIG_CAVIUM_OCTEON_SOC[0m
help
Support for error detection and correction on the
Cavium Octeon family of SOCs.
config [31mCONFIG_EDAC_ALTERA[0m
bool "Altera SOCFPGA ECC"
depends on [31mCONFIG_EDAC_MM_EDAC[0m=y && [31mCONFIG_ARCH_SOCFPGA[0m
help
Support for error detection and correction on the
Altera SOCs. This must be selected for SDRAM ECC.
Note that the preloader must initialize the SDRAM
before loading the kernel.
config [31mCONFIG_EDAC_ALTERA_L2C[0m
bool "Altera L2 Cache ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_CACHE_L2X0[0m
help
Support for error detection and correction on the
Altera L2 cache Memory for Altera SoCs. This option
requires L2 cache.
config [31mCONFIG_EDAC_ALTERA_OCRAM[0m
bool "Altera On-Chip RAM ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_SRAM[0m && [31mCONFIG_GENERIC_ALLOCATOR[0m
help
Support for error detection and correction on the
Altera On-Chip RAM Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_ETHERNET[0m
bool "Altera Ethernet FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y
help
Support for error detection and correction on the
Altera Ethernet FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_NAND[0m
bool "Altera NAND FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_MTD_NAND_DENALI[0m
help
Support for error detection and correction on the
Altera NAND FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_DMA[0m
bool "Altera DMA FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_PL330_DMA[0m=y
help
Support for error detection and correction on the
Altera DMA FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_USB[0m
bool "Altera USB FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_USB_DWC2[0m
help
Support for error detection and correction on the
Altera [31mCONFIG_USB[0m FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_QSPI[0m
bool "Altera QSPI FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_SPI_CADENCE_QUADSPI[0m
help
Support for error detection and correction on the
Altera QSPI FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_ALTERA_SDMMC[0m
bool "Altera SDMMC FIFO ECC"
depends on [31mCONFIG_EDAC_ALTERA[0m=y && [31mCONFIG_MMC_DW[0m
help
Support for error detection and correction on the
Altera SDMMC FIFO Memory for Altera SoCs.
config [31mCONFIG_EDAC_SYNOPSYS[0m
tristate "Synopsys DDR Memory Controller"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && [31mCONFIG_ARCH_ZYNQ[0m
help
Support for error detection and correction on the Synopsys [31mCONFIG_DDR[0m
memory controller.
config [31mCONFIG_EDAC_XGENE[0m
tristate "APM X-Gene SoC"
depends on [31mCONFIG_EDAC_MM_EDAC[0m && ([31mCONFIG_ARM64[0m || [31mCONFIG_COMPILE_TEST[0m)
help
Support for error detection and correction on the
[31mCONFIG_APM[0m X-Gene family of SOCs.
endif # [31mCONFIG_EDAC[0m