# # Intel pin control drivers # config [31mCONFIG_PINCTRL_BAYTRAIL[0m bool "Intel Baytrail GPIO pin control" depends on [31mCONFIG_GPIOLIB[0m && [31mCONFIG_ACPI[0m select [31mCONFIG_GPIOLIB_IRQCHIP[0m select [31mCONFIG_PINMUX[0m select [31mCONFIG_PINCONF[0m select [31mCONFIG_GENERIC_PINCONF[0m help driver for memory mapped GPIO functionality on Intel Baytrail platforms. Supports 3 banks with 102, 28 and 44 gpios. Most pins are usually muxed to some other functionality by firmware, so only a small amount is available for gpio use. Requires [31mCONFIG_ACPI[0m device enumeration code to set up a platform device. config [31mCONFIG_PINCTRL_CHERRYVIEW[0m tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" depends on [31mCONFIG_ACPI[0m select [31mCONFIG_PINMUX[0m select [31mCONFIG_PINCONF[0m select [31mCONFIG_GENERIC_PINCONF[0m select [31mCONFIG_GPIOLIB[0m select [31mCONFIG_GPIOLIB_IRQCHIP[0m help Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. config [31mCONFIG_PINCTRL_MERRIFIELD[0m tristate "Intel Merrifield pinctrl driver" depends on [31mCONFIG_X86_INTEL_MID[0m select [31mCONFIG_PINMUX[0m select [31mCONFIG_PINCONF[0m select [31mCONFIG_GENERIC_PINCONF[0m help Merrifield Family-Level Interface Shim (FLIS) driver provides an interface that allows configuring of SoC pins and using them as GPIOs. config [31mCONFIG_PINCTRL_INTEL[0m tristate select [31mCONFIG_PINMUX[0m select [31mCONFIG_PINCONF[0m select [31mCONFIG_GENERIC_PINCONF[0m select [31mCONFIG_GPIOLIB[0m select [31mCONFIG_GPIOLIB_IRQCHIP[0m config [31mCONFIG_PINCTRL_BROXTON[0m tristate "Intel Broxton pinctrl and GPIO driver" depends on [31mCONFIG_ACPI[0m select [31mCONFIG_PINCTRL_INTEL[0m help Broxton pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. config [31mCONFIG_PINCTRL_SUNRISEPOINT[0m tristate "Intel Sunrisepoint pinctrl and GPIO driver" depends on [31mCONFIG_ACPI[0m select [31mCONFIG_PINCTRL_INTEL[0m help Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver provides an interface that allows configuring of PCH pins and using them as GPIOs. |