config [31mCONFIG_WILC1000[0m tristate ---help--- This module only support IEEE 802.11n WiFi. config [31mCONFIG_WILC1000_SDIO[0m tristate "Atmel WILC1000 SDIO (WiFi only)" depends on [31mCONFIG_CFG80211[0m && [31mCONFIG_INET[0m && [31mCONFIG_MMC[0m select [31mCONFIG_WILC1000[0m ---help--- This module adds support for the SDIO interface of adapters using [31mCONFIG_WILC1000[0m chipset. The Atmel [31mCONFIG_WILC1000[0m SDIO is a full speed interface. It meets SDIO card specification version 2.0. The interface supports the 1-bit/4-bit SD transfer mode at the clock range of 0-50 MHz. The host can use this interface to read and write from any register within the chip as well as configure the [31mCONFIG_WILC1000[0m for data DMA. To use this interface, pin9 (SDIO_SPI_CFG) must be grounded. Select this if your platform is using the SDIO bus. config [31mCONFIG_WILC1000_SPI[0m tristate "Atmel WILC1000 SPI (WiFi only)" depends on [31mCONFIG_CFG80211[0m && [31mCONFIG_INET[0m && [31mCONFIG_SPI[0m select [31mCONFIG_WILC1000[0m ---help--- This module adds support for the [31mCONFIG_SPI[0m interface of adapters using [31mCONFIG_WILC1000[0m chipset. The Atmel [31mCONFIG_WILC1000[0m has a Serial Peripheral Interface ([31mCONFIG_SPI[0m) that operates as a [31mCONFIG_SPI[0m slave. This [31mCONFIG_SPI[0m interface can be used for control and for serial I/O of 802.11 data. The [31mCONFIG_SPI[0m is a full-duplex slave synchronous serial interface that is available immediately following reset when pin 9 (SDIO_SPI_CFG) is tied to VDDIO. Select this if your platform is using the [31mCONFIG_SPI[0m bus. config [31mCONFIG_WILC1000_HW_OOB_INTR[0m bool "WILC1000 out of band interrupt" depends on [31mCONFIG_WILC1000_SDIO[0m default n ---help--- This option enables out-of-band interrupt support for the [31mCONFIG_WILC1000[0m chipset. This OOB interrupt is intended to provide a faster interrupt mechanism for SDIO host controllers that don't support SDIO interrupt. Select this option If the SDIO host controller in your platform doesn't support SDIO time devision interrupt. |