1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 | /* * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #ifndef __LINUX_CLK_TEGRA_H_ #define __LINUX_CLK_TEGRA_H_ #include <linux/types.h> #include <linux/bug.h> /* * Tegra CPU clock and reset control ops * * wait_for_reset: * keep waiting until the CPU in reset state * put_in_reset: * put the CPU in reset state * out_of_reset: * release the CPU from reset state * enable_clock: * CPU clock un-gate * disable_clock: * CPU clock gate * rail_off_ready: * CPU is ready for rail off * suspend: * save the clock settings when CPU go into low-power state * resume: * restore the clock settings when CPU exit low-power state */ struct tegra_cpu_car_ops { void (*wait_for_reset)(u32 cpu); void (*put_in_reset)(u32 cpu); void (*out_of_reset)(u32 cpu); void (*enable_clock)(u32 cpu); void (*disable_clock)(u32 cpu); #ifdef [31mCONFIG_PM_SLEEP[0m bool (*rail_off_ready)(void); void (*suspend)(void); void (*resume)(void); #endif }; extern struct tegra_cpu_car_ops *tegra_cpu_car_ops; static inline void tegra_wait_cpu_in_reset(u32 cpu) { if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset)) return; tegra_cpu_car_ops->wait_for_reset(cpu); } static inline void tegra_put_cpu_in_reset(u32 cpu) { if (WARN_ON(!tegra_cpu_car_ops->put_in_reset)) return; tegra_cpu_car_ops->put_in_reset(cpu); } static inline void tegra_cpu_out_of_reset(u32 cpu) { if (WARN_ON(!tegra_cpu_car_ops->out_of_reset)) return; tegra_cpu_car_ops->out_of_reset(cpu); } static inline void tegra_enable_cpu_clock(u32 cpu) { if (WARN_ON(!tegra_cpu_car_ops->enable_clock)) return; tegra_cpu_car_ops->enable_clock(cpu); } static inline void tegra_disable_cpu_clock(u32 cpu) { if (WARN_ON(!tegra_cpu_car_ops->disable_clock)) return; tegra_cpu_car_ops->disable_clock(cpu); } #ifdef [31mCONFIG_PM_SLEEP[0m static inline bool tegra_cpu_rail_off_ready(void) { if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready)) return false; return tegra_cpu_car_ops->rail_off_ready(); } static inline void tegra_cpu_clock_suspend(void) { if (WARN_ON(!tegra_cpu_car_ops->suspend)) return; tegra_cpu_car_ops->suspend(); } static inline void tegra_cpu_clock_resume(void) { if (WARN_ON(!tegra_cpu_car_ops->resume)) return; tegra_cpu_car_ops->resume(); } #endif extern void tegra210_xusb_pll_hw_control_enable(void); extern void tegra210_xusb_pll_hw_sequence_start(void); extern void tegra210_sata_pll_hw_control_enable(void); extern void tegra210_sata_pll_hw_sequence_start(void); #endif /* __LINUX_CLK_TEGRA_H_ */ |