if ([31mCONFIG_BF561[0m)
source "arch/blackfin/mach-bf561/boards/Kconfig"
menu "BF561 Specific Configuration"
if (![31mCONFIG_SMP[0m)
comment "Core B Support"
config [31mCONFIG_BF561_COREB[0m
bool "Enable Core B loader"
default y
endif
comment "Interrupt Priority Assignment"
menu "Priority"
config [31mCONFIG_IRQ_PLL_WAKEUP[0m
int "PLL Wakeup Interrupt"
default 7
config [31mCONFIG_IRQ_DMA1_ERROR[0m
int "DMA1 Error (generic)"
default 7
config [31mCONFIG_IRQ_DMA2_ERROR[0m
int "DMA2 Error (generic)"
default 7
config [31mCONFIG_IRQ_IMDMA_ERROR[0m
int "IMDMA Error (generic)"
default 7
config [31mCONFIG_IRQ_PPI0_ERROR[0m
int "PPI0 Error Interrupt"
default 7
config [31mCONFIG_IRQ_PPI1_ERROR[0m
int "PPI1 Error Interrupt"
default 7
config [31mCONFIG_IRQ_SPORT0_ERROR[0m
int "SPORT0 Error Interrupt"
default 7
config [31mCONFIG_IRQ_SPORT1_ERROR[0m
int "SPORT1 Error Interrupt"
default 7
config [31mCONFIG_IRQ_SPI_ERROR[0m
int "SPI Error Interrupt"
default 7
config [31mCONFIG_IRQ_UART_ERROR[0m
int "UART Error Interrupt"
default 7
config [31mCONFIG_IRQ_RESERVED_ERROR[0m
int "Reserved Interrupt"
default 7
config [31mCONFIG_IRQ_DMA1_0[0m
int "DMA1 0 Interrupt(PPI1)"
default 8
config [31mCONFIG_IRQ_DMA1_1[0m
int "DMA1 1 Interrupt(PPI2)"
default 8
config [31mCONFIG_IRQ_DMA1_2[0m
int "DMA1 2 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_3[0m
int "DMA1 3 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_4[0m
int "DMA1 4 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_5[0m
int "DMA1 5 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_6[0m
int "DMA1 6 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_7[0m
int "DMA1 7 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_8[0m
int "DMA1 8 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_9[0m
int "DMA1 9 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_10[0m
int "DMA1 10 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA1_11[0m
int "DMA1 11 Interrupt"
default 8
config [31mCONFIG_IRQ_DMA2_0[0m
int "DMA2 0 (SPORT0 RX)"
default 9
config [31mCONFIG_IRQ_DMA2_1[0m
int "DMA2 1 (SPORT0 TX)"
default 9
config [31mCONFIG_IRQ_DMA2_2[0m
int "DMA2 2 (SPORT1 RX)"
default 9
config [31mCONFIG_IRQ_DMA2_3[0m
int "DMA2 3 (SPORT2 TX)"
default 9
config [31mCONFIG_IRQ_DMA2_4[0m
int "DMA2 4 (SPI)"
default 9
config [31mCONFIG_IRQ_DMA2_5[0m
int "DMA2 5 (UART RX)"
default 9
config [31mCONFIG_IRQ_DMA2_6[0m
int "DMA2 6 (UART TX)"
default 9
config [31mCONFIG_IRQ_DMA2_7[0m
int "DMA2 7 Interrupt"
default 9
config [31mCONFIG_IRQ_DMA2_8[0m
int "DMA2 8 Interrupt"
default 9
config [31mCONFIG_IRQ_DMA2_9[0m
int "DMA2 9 Interrupt"
default 9
config [31mCONFIG_IRQ_DMA2_10[0m
int "DMA2 10 Interrupt"
default 9
config [31mCONFIG_IRQ_DMA2_11[0m
int "DMA2 11 Interrupt"
default 9
config [31mCONFIG_IRQ_TIMER0[0m
int "TIMER 0 Interrupt"
default 7 if [31mCONFIG_TICKSOURCE_GPTMR0[0m
default 8
config [31mCONFIG_IRQ_TIMER1[0m
int "TIMER 1 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER2[0m
int "TIMER 2 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER3[0m
int "TIMER 3 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER4[0m
int "TIMER 4 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER5[0m
int "TIMER 5 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER6[0m
int "TIMER 6 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER7[0m
int "TIMER 7 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER8[0m
int "TIMER 8 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER9[0m
int "TIMER 9 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER10[0m
int "TIMER 10 Interrupt"
default 10
config [31mCONFIG_IRQ_TIMER11[0m
int "TIMER 11 Interrupt"
default 10
config [31mCONFIG_IRQ_PROG0_INTA[0m
int "Programmable Flags0 A (8)"
default 11
config [31mCONFIG_IRQ_PROG0_INTB[0m
int "Programmable Flags0 B (8)"
default 11
config [31mCONFIG_IRQ_PROG1_INTA[0m
int "Programmable Flags1 A (8)"
default 11
config [31mCONFIG_IRQ_PROG1_INTB[0m
int "Programmable Flags1 B (8)"
default 11
config [31mCONFIG_IRQ_PROG2_INTA[0m
int "Programmable Flags2 A (8)"
default 11
config [31mCONFIG_IRQ_PROG2_INTB[0m
int "Programmable Flags2 B (8)"
default 11
config [31mCONFIG_IRQ_DMA1_WRRD0[0m
int "MDMA1 0 write/read INT"
default 8
config [31mCONFIG_IRQ_DMA1_WRRD1[0m
int "MDMA1 1 write/read INT"
default 8
config [31mCONFIG_IRQ_DMA2_WRRD0[0m
int "MDMA2 0 write/read INT"
default 9
config [31mCONFIG_IRQ_DMA2_WRRD1[0m
int "MDMA2 1 write/read INT"
default 9
config [31mCONFIG_IRQ_IMDMA_WRRD0[0m
int "IMDMA 0 write/read INT"
default 12
config [31mCONFIG_IRQ_IMDMA_WRRD1[0m
int "IMDMA 1 write/read INT"
default 12
config [31mCONFIG_IRQ_WDTIMER[0m
int "Watch Dog Timer"
default 13
help
Enter the priority numbers between 7-13 ONLY. Others are Reserved.
This applies to all the above. It is not recommended to assign the
highest priority number 7 to UART or any other device.
endmenu
endmenu
endif